Stacked PIN Diode Switch Structure for Self-Matched Linearity
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Solution Overview
Problem
Existing semiconductor switch devices face challenges in linearity optimization due to parameter mismatches between PIN diodes, which are exacerbated by variations in semiconductor processes across different batches and wafers, leading to reduced circuit performance and increased costs.
Innovation Solution
A semiconductor switch device is designed with a stacked structure of two PIN diodes, where the first intrinsic layer and second intrinsic layer have the same thickness and doping concentration, forming a geometrically centrosymmetric pattern, allowing for parameter self-matching and improved linearity, while reducing chip packaging costs by doubling the number of PIN diodes in the same area.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If discrete PIN diodes are used in separate packages, then device flexibility is improved, but parameter matching precision deteriorates due to process variations
Solution Approach 1:
The patent combines multiple PIN diodes into a single integrated chip structure, where first and second PIN diodes are formed on the same semiconductor substrate with shared layers. This merging approach ensures that all diodes experience identical process conditions, eliminating parameter mismatches caused by batch-to-batch variations while maintaining design flexibility through integrated circuit configuration options.
Solution Approach 2:
The integrated chip structure provides multi-functionality by supporting various connection configurations (series, parallel, common-anode, common-cathode) within a single device. This universal design allows the same chip to serve multiple circuit functions without requiring separate discrete components, thereby improving both parameter matching and application versatility.
2Manufacturing precision
If multiple PIN diodes are integrated in one chip, then parameter matching is improved, but device complexity increases
Solution Approach 1:
The patent segments the integrated chip into distinct functional regions with clearly defined first and second PIN diode structures. Each diode maintains its own intrinsic layer and semiconductor layers, allowing independent electrical characteristics while sharing common substrate resources. This segmentation approach simplifies the fabrication process and device characterization compared to fully monolithic structures.
Solution Approach 2:
The patent transitions from planar integration to a stacked three-dimensional layer structure, where intrinsic layers and semiconductor layers are arranged in vertical sequences. This dimensional change allows multiple diodes to be integrated without increasing lateral footprint, reducing device complexity while maintaining precise parameter matching through vertical stacking geometry.
3Ease of manufacture
If conventional integration methods are used, then manufacturing simplicity is improved, but area efficiency deteriorates
Solution Approach 1:
The patent implements a nested layer structure where intrinsic layers and semiconductor layers are stacked sequentially to form compact diode units. The first and second PIN diodes share common substrate layers and can be arranged in a nested configuration, maximizing the use of vertical space and achieving high area efficiency while maintaining straightforward fabrication processes.
Data Source
AI summary
This application provides a semiconductor switch device and a preparation method thereof, and a solid-state phase shifter. The semiconductor switch device includes a second semiconductor layer, a first intrinsic layer, a first semiconductor layer, a second intrinsic layer, and a third semiconductor layer that are stacked in a sandwich structure. The first intrinsic layer is located between the second semiconductor layer and the first semiconductor layer, and the first intrinsic layer, the second semiconductor layer, and the first semiconductor layer form a first PIN diode. The second intrinsic layer is located between the third semiconductor layer and the first semiconductor layer, and the second intrinsic layer, the third semiconductor layer, and the first semiconductor layer form a second PIN diode. The first PIN diode and the second PIN diode are axisymmetrically disposed.