Stacked Pixel Capacitor Circuit for High-Frequency Displays
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Solution Overview
Problem
The increasing complexity of pixel structures in display devices to achieve high-frequency operation and high-resolution imaging requires efficient stacking of lines and electrodes, while maintaining process efficiency and insulating layers to prevent metal layer interference.
Innovation Solution
A pixel circuit design that includes a first and second capacitor formed by overlapping electrodes with a gate electrode or active pattern, allowing for reduced additional process steps in forming these electrodes and ensuring sufficient insulating layer thickness for effective metal layer separation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If the number of lines and electrodes in the pixel structure is increased to drive the display device at high frequency, then the operating frequency is improved, but the area of the pixel structure increases
Solution Approach 1:
The patent transitions from a planar arrangement of lines and electrodes to a three-dimensional stacked structure. Multiple electrode layers are positioned at different heights (Z-dimension) and overlapped in the planar view, enabling high-frequency operation without increasing the pixel area footprint.
Solution Approach 2:
The patent implements a nested configuration where multiple electrode layers are stacked vertically within the same planar footprint. The first upper electrode and second lower electrode are positioned in overlapping regions, creating a compact nested structure that maximizes functionality within limited space.
2Area of stationary object
If the pixel structure is compacted to display high resolution images, then the area is reduced, but the insulating layer thickness becomes insufficient preventing metal layer interference
Solution Approach 1:
By utilizing the vertical dimension for stacking electrode layers, the patent maintains adequate insulating layer thickness between metal layers while reducing the planar area. The insulating layers are positioned between stacked electrodes in the Z-dimension, ensuring proper isolation without compromising pixel area.
3Adaptability or versatility
If additional electrodes are added to the pixel structure, then the functionality is improved, but the number of process steps increases
Solution Approach 1:
The patent combines the formation of capacitor electrodes with the formation of transistor electrodes into unified process steps. The first upper electrode serves both as a capacitor electrode and is formed during the same photolithography and etching processes used for transistor gate structures, thereby adding functionality without proportionally increasing process steps.
Solution Approach 2:
The electrode structures serve multiple functions simultaneously. The first upper electrode and second lower electrode act as both capacitor electrodes for charge storage and as part of the transistor structure, enabling dual functionality from single process steps.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This design enhances the efficiency of electrode formation, reduces the number of process steps, and secures a sufficient charge margin by using capacitors connected in parallel, effectively insulating vertically stacked metal layers.
Implementation Method 1
a first upper electrode disposed on the first lower electrode, overlapping the first lower electrode in a plan view, including a silicon semiconductor, and constituting a first capacitor together with the first lower electrode
Implementation Method 2
a second upper electrode disposed on the second lower electrode, overlapping the second lower electrode in a plan view, including an oxide semiconductor, and constituting a second capacitor together with the second lower electrode
Data Source
AI summary
A display device includes a first lower electrode disposed on a base substrate, a first upper electrode disposed on the first lower electrode, overlapping the first lower electrode in a plan view, including a silicon semiconductor, and constituting a first capacitor together with the first lower electrode, a second lower electrode disposed on the first upper electrode, and a second upper electrode disposed on the second lower electrode, overlapping the second lower electrode in a plan view, including an oxide semiconductor, and constituting a second capacitor together with the second lower electrode.