Stacked Pixel Capacitor Layout for High-Dynamic-Range Image Sensing
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Solution Overview
Problem
Existing image sensing devices face challenges in achieving a high dynamic range while maintaining a reduced pixel size, particularly in CMOS image sensing devices.
Innovation Solution
The image sensing device incorporates a capacitor structure with through silicon vias (TSVs) and a floating diffusion region, coupled by a switch transistor gate, to enhance capacitance and store overflow charges, along with a stacked photoelectric conversion region and transistor gates to optimize light conversion and signal amplification.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If the pixel size is reduced to increase the number of pixels, then the area per pixel is reduced, but the dynamic range deteriorates due to insufficient capacitance for storing photocharges
Solution Approach 1:
The patent transitions from a planar capacitor structure to a three-dimensional stacked structure. The capacitor is formed between the first substrate layer and the second substrate layer, utilizing the vertical dimension (thickness direction) to increase capacitance. This allows the capacitor to store more photocharges without increasing the horizontal pixel area, thereby maintaining small pixel size while improving dynamic range.
Solution Approach 2:
The capacitor structure is nested within the stacked substrate configuration. The first substrate layer containing the photoelectric conversion region and floating diffusion region is positioned directly above the second substrate layer containing the capacitor electrodes. This nested arrangement maximizes space utilization within the pixel structure, allowing the capacitor to be integrated without increasing the overall pixel footprint.
2Reliability
If the capacitance is increased to improve dynamic range, then the capacitor size increases, but the pixel size increases accordingly
Solution Approach 1:
The invention resolves this contradiction by moving the capacitance increase from the horizontal plane to the vertical dimension. The capacitor utilizes the space between the first and second substrate layers (thickness direction) to achieve high capacitance. This allows the capacitor to store sufficient photocharges for improved dynamic range while maintaining a compact horizontal footprint that keeps pixel size reduced.
3Reliability
If more circuit components are added to improve functionality, then the image quality is improved, but the device complexity increases
Solution Approach 1:
The patent merges multiple functions into the stacked substrate structure. The first substrate layer integrates the photoelectric conversion region, floating diffusion region, and switch transistor gate. The second substrate layer integrates the capacitor electrodes and interconnect structures. This merging of functions across layers reduces the need for separate discrete components and simplifies the overall device architecture while maintaining high image quality through improved photocharge storage and management.
Solution Approach 2:
By utilizing the vertical stacking dimension, the patent accommodates multiple circuit components and structures without increasing horizontal complexity. The through-silicon vias and interconnect layers provide vertical connectivity that reduces the need for complex lateral routing, thereby improving functionality while keeping the device structure manageable.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration ensures a high dynamic range while minimizing pixel size, reducing noise, and preventing leakage currents, thereby improving image quality and efficiency.
Implementation Method 1
a first substrate layer including a photoelectric conversion region for converting incident light into photocharges
Data Source
AI summary
An image sensing device includes a first substrate layer including a photoelectric conversion region for converting incident light into photocharges and a floating diffusion region for storing the photocharges therein, a first interconnect layer disposed over the first substrate layer and including a switch transistor gate overlapping at least a portion of the floating diffusion region, a second substrate layer disposed over the first interconnect layer, a second interconnect layer disposed over the second substrate layer, and a capacitor electrically coupled to the floating diffusion region by the switch transistor gate. The capacitor includes first and second electrodes that are disposed across the first interconnect layer, the second substrate layer, and the second interconnect layer, wherein a portion of the first interconnect layer, a portion of the second substrate layer, and a portion of the second interconnect layer are disposed between the first electrode and the second electrode.