Stacked Pixel Capacitor Above TFT for Display Backplane
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Solution Overview
Problem
Existing display technologies face challenges in optimizing pixel capacitance and production yield due to the thick inter-layer dielectric layer, which affects the area and parasitic capacitance, leading to reduced display panel definition and potential short circuits.
Innovation Solution
A display backplane design where the thin film transistor and pixel capacitor assembly are configured at different layers, with the pixel capacitor assembly positioned over the thin film transistor, reducing parasitic capacitance and increasing aperture ratio, and using a thinner passivation layer to improve on-state current and production yield.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the inter-layer dielectric layer is made thick to ensure insulation, then the production yield is improved, but the pixel capacitor area must be increased to maintain required capacitance value, which reduces the definition of the display panel
Solution Approach 1:
The patent transitions from a planar configuration where the pixel capacitor and TFT are on the same layer to a three-dimensional stacked configuration where the pixel capacitor is positioned above the TFT. This vertical stacking allows the pixel capacitor to occupy the space above the TFT rather than competing for lateral space, thereby reducing the pixel capacitor area while maintaining the required capacitance value through the thicker ILD layer.
2Reliability
If the inter-layer dielectric layer is made thick to ensure insulation, then short circuiting is prevented, but the pixel capacitance is reduced, requiring larger capacitor area which conflicts with definition improvement
Solution Approach 1:
By stacking the pixel capacitor vertically above the TFT, the patent enables the use of a thicker ILD layer for improved insulation without compromising pixel capacitance. The vertical arrangement separates the insulation function (handled by the thick ILD) from the capacitance function (handled by the stacked capacitor structure), resolving the trade-off between insulation performance and capacitance value.
3Quantity of substance
If the pixel capacitor portion is enlarged to compensate for parasitic capacitance, then the required capacitance value is achieved, but the aperture ratio of the pixel region is reduced
Solution Approach 1:
The patent employs vertical stacking to position the pixel capacitor above the TFT, allowing the capacitor to utilize the vertical space rather than lateral space. This enables the aperture ratio to be improved by reducing the lateral footprint of the pixel capacitor while maintaining the required capacitance value through the stacked configuration and appropriate ILD thickness.
4Area of stationary object
If the design area is reduced to improve definition, then the display panel resolution is enhanced, but the parasitic capacitance increases when using conventional planar configurations
Solution Approach 1:
By transitioning to a stacked configuration where the pixel capacitor is positioned vertically above the TFT, the patent reduces the lateral design area while minimizing parasitic capacitance. The vertical separation between the capacitor and TFT, combined with the insulating ILD layer, reduces unwanted electrical coupling and parasitic effects that would otherwise increase in smaller planar designs.
Data Source
AI summary
A display backplane includes a substrate, a thin film transistor over the substrate, and a pixel capacitor assembly over a side of the thin film transistor away from the substrate, and an orthographic projection of the pixel capacitor assembly on the substrate covers at least one portion of an orthographic projection of the thin film transistor on the substrate. The pixel capacitor assembly includes a first electrode, a passivation layer, and a second electrode, sequentially over a side of the thin film transistor away from the substrate, and an orthographic projection of the first electrode on the substrate is overlapped with the orthographic projection of the thin film transistor on the substrate. A display panel including the display backplane can further include an OLED component, arranged over a side of the pixel capacitor assembly away from the substrate.