Stacked Image Sensor Pixel Cell with Selectable Shutter Modes
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Solution Overview
Problem
Stacked CMOS image sensors face challenges with reduced pixel photosensitivity and dynamic range due to miniaturization, particularly with backside illumination technology, where long-wavelength light absorption is inadequate, and existing readout modes like rolling shutter suffer from spatial distortion and require additional components for global shutter operation.
Innovation Solution
A pixel cell design with a photodiode, transfer transistor, reset transistor, and common source amplifier on one substrate, and a readout circuit block on another, allowing for optionally selectable rolling shutter and global shutter readout modes through digital register settings, incorporating in-pixel correlated double sampling for improved signal noise and reduced pixel array size.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by moving object
If backside illumination technology is used with thin substrate (2 microns), then blue light absorption is adequate, but red light absorption becomes insufficient
Solution Approach 1:
The patent transitions from planar light absorption to three-dimensional light trapping by introducing microlens arrays and light-guiding structures that redirect and multiple-pass light through the photodiode region, effectively increasing the optical path length without increasing substrate thickness
Solution Approach 2:
The patent modifies optical parameters by varying the refractive index distribution through microlens design and light-guiding structures, optimizing light coupling and trapping efficiency for different wavelengths to improve red light absorption while maintaining blue light response
2Measurement precision
If pixel size is miniaturized to increase resolution, then higher resolution is achieved, but pixel photosensitivity and dynamic range are reduced
Solution Approach 1:
The patent divides the pixel structure into functionally optimized segments: a light-trapping optical layer, a photodiode conversion layer, and a stacked readout circuit layer, allowing each segment to be independently optimized for its specific function while maintaining compact overall dimensions
Solution Approach 2:
The patent utilizes vertical stacking in the third dimension to separate optical functions from readout circuitry, enabling larger photodiode area for improved photosensitivity while maintaining small pixel footprint through three-dimensional integration
3Device complexity
If rolling shutter mode is used, then readout is simplified, but spatial distortion occurs in the image
Solution Approach 1:
The patent implements a programmable readout architecture that can dynamically switch between rolling shutter and global shutter modes through digital register settings, allowing the system to adapt its temporal sampling behavior to match the imaging requirements and eliminate spatial distortion when needed
4Manufacturing precision
If global shutter mode is implemented, then spatial distortion is eliminated, but additional components and complexity are required
Solution Approach 1:
The patent designs a universal readout circuit architecture that can perform both rolling shutter and global shutter operations using the same hardware components, with mode selection controlled by digital registers, thereby achieving global shutter functionality without proportionally increasing device complexity
Solution Approach 2:
The patent employs dynamic control signals and programmable timing sequences that allow the same circuit hardware to flexibly switch between different readout modes, eliminating the need for dedicated global shutter components while maintaining spatial accuracy when required
5Area of stationary object
If stacked chip formation is used, then area is reduced and manufacturing flexibility is improved, but inter-chip interconnect complexity increases
Solution Approach 1:
The patent segments the sensor into functionally distinct chips: a sensor chip optimized for light detection and a circuit chip optimized for signal processing, connected through standardized inter-chip interfaces that reduce interconnect complexity through modular design
Solution Approach 2:
The patent introduces standardized interface layers and bonding structures as intermediaries between the sensor chip and circuit chip, providing organized signal routing and reducing the complexity of direct inter-chip interconnections through structured communication protocols
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This design enhances image sensor performance by enabling flexible readout modes, reducing pixel array size and manufacturing costs, and maintaining high dynamic range while minimizing spatial distortion and power consumption.
Implementation Method 1
the image sensor converts the light into electrical signals
Data Source
AI summary
A pixel cell has a photodiode, a transfer transistor, a reset transistor, an amplifier transistor in a common source configuration and a readout circuit block. The photodiode, transfer transistor, reset transistor and common source amplifier are disposed within a first substrate of a first semiconductor chip for accumulating an image charge in response to light incident upon the photodiode. The readout circuit block may be partially disposed within a second substrate of a second semiconductor chip and partially disposed within the first substrate wherein the readout circuit block comprises optionally selectable rolling shutter and global shutter readout modes through the use of computer programmable digital register settings. The global shutter readout mode provides in-pixel correlated double sampling.