Stacked Photoelectric Conversion Pixel Structure for Low Dark Current
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing photoelectric conversion devices face challenges in achieving higher pixel density and suppressing stress-induced dark current due to the lack of alignment in plane orientations of silicon substrates, which affects the bonding process and overall device performance.
Innovation Solution
The proposed solution involves stacking substrates with the same plane orientation for the first and second semiconductor layers and matching the orientation of the third semiconductor layer, ensuring that the second substrate is between the first and third substrates, with through wiring lines for electrical connection, to suppress stress generation and improve pixel circuit and logic circuit performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If substrates are stacked with different plane orientations to achieve higher pixel density, then pixel density is improved, but stress-induced dark current increases
Solution Approach 1:
The patent changes the plane orientation parameter of the silicon substrates, specifically using <100> oriented substrates for both the first and second substrates, and <110> oriented substrate for the third substrate. This parameter change optimizes the crystal orientation to minimize stress-induced dark current while maintaining high pixel density through the stacked configuration.
Solution Approach 2:
The patent applies different plane orientations to different substrates in the stack based on their specific functional requirements. The first and second substrates (photoelectric conversion and pixel circuit) use <100> orientation for low dark current, while the third substrate (logic circuit) uses <110> orientation, creating local optimization for each layer's performance.
2Device complexity
If substrates are stacked with misaligned plane orientations, then device integration is achieved, but bonding process quality deteriorates
Solution Approach 1:
The patent standardizes the plane orientation parameter for the first and second substrates to <100>, which facilitates better bonding alignment and process quality. This parameter consistency simplifies the bonding process while maintaining the integrated three-substrate device structure.
3Adaptability or versatility
If different plane orientations are used for stacked substrates, then functional differentiation is achieved, but stress generation increases
Solution Approach 1:
The patent applies different plane orientations locally to specific substrates based on their functional requirements: <100> orientation for photoelectric conversion and pixel circuit (low stress), and <110> orientation for logic circuit (functional differentiation). This local differentiation achieves functional versatility while minimizing overall stress generation through careful selection of orientations for each layer.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration enhances pixel density, reduces dark current, and improves the operational characteristics of the photoelectric conversion device by aligning silicon substrates and minimizing stress during bonding, leading to better imaging performance in both bright and dark conditions.
Implementation Method 1
a photoelectric conversion unit configured to generate charges in accordance with exposure to light
Data Source
AI summary
A photoelectric conversion device includes a first substrate including, in a first semiconductor layer, a photoelectric conversion unit and a transfer transistor configured to transfer charges generated in the photoelectric conversion unit, a second substrate including, in a second semiconductor layer, a pixel circuit configured to output a signal based on the charges transferred from the transfer transistor, and a third substrate including, in a third semiconductor layer, a logic circuit configured to process the signal, wherein the first, second and third substrates are stacked in such a way that the second substrate is disposed between the first substrate and the third substrate, wherein the first substrate and the second substrate are electrically connected by a through wiring line penetrating through an insulator included in the second semiconductor layer, and wherein a plane orientation of the first semiconductor layer and a plane orientation of the second semiconductor layer are same.