Stacked Image Sensor Pixel Architecture for HDR Reliability

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Solution Overview

Problem

The introduction of a capacitor in image sensors leads to reliability issues and challenges in maintaining dynamic range and signal-to-noise ratio, particularly due to motion artifacts and LED flicker problems caused by different exposure times in multi-exposure methods.

Innovation Solution

The image sensor design incorporates a split photodiode structure with a capacitor, where a small photodiode and a large photodiode operate in different illumination ranges, with a switching transistor and floating diffusion nodes to manage charge overflow and conversion gain, and a capacitor is placed on a separate semiconductor chip to prevent contamination and address overflow issues.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Adaptability or versatility

If a capacitor is added to a pixel to increase dynamic range, then the dynamic range is improved, but the reliability deteriorates due to process issues

Engineering Contradiction:
Improvedynamic rangeVSAvoidreliability
Core Design Contradiction:
Adaptability or versatilityVSReliability

Solution Approach 1:

The image sensor is divided into multiple semiconductor chips: a first chip containing the pixel array, a second chip containing the capacitor, and a third chip containing logic devices. This segmentation isolates the capacitor from the pixel fabrication process, thereby improving reliability while maintaining dynamic range enhancement capabilities.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

A dual-layer wiring structure acts as an intermediary to connect the pixel array on the first chip to the capacitor on the second chip and logic devices on the third chip. This intermediary wiring system enables functional integration across separate chips, resolving the contradiction between adding capacitor functionality and maintaining process reliability.

Inventive Principle:
Principle #24Intermediary (Mediator)

2Adaptability or versatility

If multiple floating diffusion nodes are used to manage charge storage, then the dynamic range is improved, but the device complexity increases

Engineering Contradiction:
Improvedynamic rangeVSAvoiddevice complexity
Core Design Contradiction:
Adaptability or versatilityVSDevice complexity

Solution Approach 1:

The floating diffusion nodes are distributed across different chips: first and second floating diffusion nodes are on the first semiconductor chip, while the third floating diffusion node is on the second semiconductor chip. This segmentation of charge storage nodes manages complexity by distributing functionality across separate fabrication processes.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent transitions from a single-plane pixel structure to a three-dimensional stacked architecture with multiple chips connected via wiring structures. This dimensional change allows multiple floating diffusion nodes to be implemented without increasing in-plane device complexity, as nodes are distributed across different spatial layers.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

3Reliability

If the first switching transistor is formed on the second semiconductor substrate, then charge overflow is managed effectively, but the manufacturing complexity increases

Engineering Contradiction:
Improvecharge overflow managementVSAvoidmanufacturing complexity
Core Design Contradiction:
ReliabilityVSEase of manufacture

Solution Approach 1:

The first switching transistor is extracted from the pixel array chip and formed on the second semiconductor substrate. This extraction separates the switching function from the photodetection function, enabling independent optimization of each component's fabrication process while effectively managing charge overflow through dedicated transistor placement.

Inventive Principle:
Principle #2Taking out (Extraction)

Solution Approach 2:

The dual-layer wiring structure serves as an intermediary that connects the first switching transistor on the second chip to the floating diffusion nodes on both the first and second chips. This intermediary wiring system manages the increased manufacturing complexity by providing organized inter-chip connections.

Inventive Principle:
Principle #24Intermediary (Mediator)

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This design enhances the dynamic range and reliability of image sensors by allowing dual conversion gain modes and preventing pixel contamination, while maintaining high dynamic range imaging with clear representation of both bright and dark regions.

Implementation Method 1

An image sensor may generate an image of an object using a photoelectric conversion element reacting in response to intensity of light reflected from the object

Methodology Applied
Scientific EffectPhotoelectric conversion: Photoelectric Effect

Data Source

PatentUS20240072092A1Image sensor
Publication Date: 2024.02.29 SAMSUNG ELECTRONICS CO LTD
  • US20240072092A1 patent drawing
  • US20240072092A1 patent drawing
  • US20240072092A1 patent drawing

AI summary

An image sensor includes a first chip including a first substrate having a plurality of pixels, and a first wiring structure, each of the plurality of pixels including first and second isolated photodiodes; a second chip including a second wiring structure, and a second substrate; and a third chip including a third wiring structure, and a third substrate having logic devices, wherein each of the plurality of pixels includes a first floating diffusion node on the first photodiode, a second floating diffusion node on the second photodiode, a third floating diffusion node between the first and second floating diffusion nodes on the second photodiode, and a first switching transistor on the second substrate, and wherein the first switching transistor is connected to the first floating diffusion node through the first and second wiring structures, and the third floating diffusion node through the first and second wiring structures.