Stacked Pixel Architecture for Flexible Solid-State Imaging

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Solution Overview

Problem

Current solid-state imaging devices lack flexibility in design, particularly in the integration of photoelectric converters and pixel transistors, which limits their performance and adaptability.

Innovation Solution

A solid-state imaging device with a stacked structure of semiconductor layers, where a first semiconductor layer includes a photoelectric converter and an electric charge accumulation section, and a second semiconductor layer with a pixel transistor is stacked on the first layer, featuring a pixel separation section, insulating regions, through electrodes, and coupling sections to enhance electrical coupling and design flexibility.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Adaptability or versatility

If photoelectric converter and pixel transistor are integrated in the same semiconductor layer, then device complexity is reduced, but design flexibility and performance optimization are limited

Engineering Contradiction:
Improvedesign flexibilityVSAvoidstructure complexity
Core Design Contradiction:
Adaptability or versatilityVSDevice complexity

Solution Approach 1:

The device is divided into two separate semiconductor layers: a first semiconductor layer containing the photoelectric converter and charge accumulation section, and a second semiconductor layer containing the pixel transistor. This segmentation allows independent optimization of each layer's design and performance characteristics while maintaining functional integration through vertical stacking and electrical coupling via through-electrodes.

Inventive Principle:
Principle #1Segmentation

2Adaptability or versatility

If photoelectric converter and pixel transistor are separated into different layers, then design flexibility is improved, but manufacturing complexity increases

Engineering Contradiction:
Improvedesign flexibilityVSAvoidmanufacturing complexity
Core Design Contradiction:
Adaptability or versatilityVSEase of manufacture

Solution Approach 1:

The patent transitions from planar integration to three-dimensional vertical stacking, separating the photoelectric converter and pixel transistor into different layers along the vertical dimension. This dimensional change enables independent fabrication of each layer using standard CMOS processes, followed by wafer bonding to assemble the stacked structure, thereby maintaining manufacturing feasibility while achieving design flexibility.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

3Productivity

If stacked structure with multiple semiconductor layers is used, then design flexibility and signal processing efficiency are improved, but electrical coupling complexity increases

Engineering Contradiction:
Improvesignal processing efficiencyVSAvoidelectrical coupling complexity
Core Design Contradiction:
ProductivityVSDevice complexity

Solution Approach 1:

The through-electrodes serving as coupling sections are designed to perform multiple functions simultaneously: they provide electrical connection between the first and second semiconductor layers, serve as charge transfer pathways from the charge accumulation section to the pixel transistor, and function as part of the overall signal readout architecture. This multi-functionality reduces the need for separate coupling structures and simplifies the overall electrical coupling system.

Inventive Principle:
Principle #6Universality (Multi-functionality)

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This configuration allows for improved flexibility in design and performance by enabling more efficient signal processing and readout of electric charges, leading to enhanced image quality and reduced noise.

Implementation Method 1

a first semiconductor layer including a photoelectric converter and an electric charge accumulation section for each pixel, the electric charge accumulation section in which a signal electric charge generated in the photoelectric converter is accumulated

Methodology Applied
Scientific EffectPhotoelectric effect: Photoelectric Effect

Data Source

PatentUS12136640B2Solid-state imaging device
Publication Date: 2024.11.05 SONY SEMICON SOLUTIONS CORP
  • US12136640B2 patent drawing
  • US12136640B2 patent drawing
  • US12136640B2 patent drawing

AI summary

There is provided a solid-state imaging device including: a first semiconductor layer including a photoelectric converter and an electric charge accumulation section for each pixel, the electric charge accumulation section in which a signal electric charge generated in the photoelectric converter is accumulated; a pixel separation section that is provided in the first semiconductor layer, and partitions a plurality of the pixels from each other; a second semiconductor layer that is provided with a pixel transistor and is stacked on the first semiconductor layer, the pixel transistor that reads the signal electric charge of the electric charge accumulation section; and a first shared coupling section that is provided between the second semiconductor layer and the first semiconductor layer, and is provided to straddle the pixel separation section and is electrically coupled to a plurality of the electric charge accumulation sections.