Stacked Pixel Circuit Layout for Low-Capacitance Imaging Sensors
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Solution Overview
Problem
In imaging devices with a three-dimensional structure, stacking three semiconductor layers can lead to increased chip size and hinder miniaturization due to electrical connections between the layers, and the connection via for the floating diffusion in pixel circuits occupies a significant area, reducing the effective region for pixel circuits.
Innovation Solution
An imaging device design featuring a first substrate with a photodiode and floating diffusion, a second substrate with a pixel circuit, and a wire that penetrates both substrates to connect the floating diffusion to an amplification transistor, with a trench on the second substrate to reduce parasitic capacitance and improve charge-voltage conversion efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If three layers of semiconductor substrates are stacked to achieve three-dimensional structure, then pixel density is improved, but chip size increases and miniaturization is hindered
Solution Approach 1:
The patent transitions from planar two-dimensional pixel arrangement to three-dimensional stacked structure by bonding multiple semiconductor substrates vertically. This dimensional change allows pixel density to increase without proportionally increasing chip area, as pixels are arranged in multiple layers along the vertical axis rather than only in the horizontal plane.
Solution Approach 2:
The patent extracts and removes unnecessary electrical connection structures between stacked substrates. By eliminating redundant wiring and connection elements, the chip size is reduced while maintaining the three-dimensional pixel arrangement, thus achieving miniaturization without sacrificing pixel density.
2Reliability
If connection via is used to connect floating diffusion to amplification transistor, then electrical connection is achieved, but effective region of pixel circuit is reduced
Solution Approach 1:
The patent removes the connection via structure that traditionally connects the floating diffusion to the amplification transistor. This extraction eliminates the parasitic capacitance and occupies no longer reduces the effective pixel circuit region, while electrical connection is maintained through alternative wiring paths on the substrate surface or through other vertical connection methods.
Solution Approach 2:
The patent changes the local connection method by replacing the vertical via connection with horizontal wiring or alternative vertical connections that do not occupy pixel circuit area. This local modification allows the floating diffusion to remain electrically connected to the amplification transistor without the via structure encroaching on the effective pixel region.
Data Source
AI summary
An imaging device of an embodiment has a first substrate, a second substrate, a wire, and a trench. The first substrate has a pixel having a photodiode and a floating diffusion that holds a charge converted by the photodiode. The second substrate has a pixel circuit that reads a pixel signal based on the charge held in the floating diffusion in the pixel, and is stacked on the first substrate. The wire penetrates the first substrate and the second substrate in a stacking direction, and electrically connects the floating diffusion in the first substrate to an amplification transistor in the pixel circuit of the second substrate. The trench is formed at least in the second substrate, runs in parallel with the wire, and has a depth equal to or greater than the thickness of a semiconductor layer in the second substrate.