Stacked Pixel Image Sensor Layout for Noise Reduction
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Solution Overview
Problem
Existing image sensors face challenges in reducing pixel size while minimizing noise, which affects image quality.
Innovation Solution
The image sensor design includes a layered structure with a top layer containing a photodiode and a transfer transistor, a middle layer with capacitors and sampling transistors, and a bottom layer with an analog-to-digital converter (ADC) circuit, optimizing signal processing and noise reduction.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If pixel size is reduced to increase resolution, then image detail capability is improved, but noise increases
Solution Approach 1:
The patent transitions from a planar pixel structure to a three-dimensional stacked structure with multiple layers (first layer with photodiode, second layer with capacitors, third layer with ADC). This vertical dimensionality change allows signal processing components to be distributed across layers, reducing in-pixel noise while maintaining small pixel footprint.
Solution Approach 2:
The pixel structure is segmented into multiple functional layers: photodiode layer for light detection, capacitor layer for signal storage and integration, and ADC layer for digital conversion. This segmentation separates noise-generating components from the photodetection process, reducing overall pixel noise while preserving detail capability.
2Measurement precision
If more signal processing components are integrated into each pixel, then image quality is improved, but pixel size increases
Solution Approach 1:
Signal processing components (capacitors, ADC circuits) are moved from the horizontal plane to the vertical dimension by placing them in separate stacked layers. This allows high-density integration of processing components without increasing the lateral pixel area, maintaining small pixel size while improving image quality through enhanced signal processing.
Solution Approach 2:
The patent implements a nested layered structure where the second layer with capacitors is positioned beneath the first layer with photodiodes, and the third layer with ADC circuits is positioned beneath the second layer. This nested arrangement allows multiple processing components to be contained within the vertical footprint of a single pixel, preventing pixel size expansion while improving image quality.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This design allows for a reduction in pixel size while effectively decreasing noise, thereby enhancing image quality and performance.
Implementation Method 1
a top layer including a photodiode included in a pixel and a transfer transistor configured to transfer an electrical signal generated by the photodiode
Data Source
AI summary
An image sensor includes: a top layer including a photodiode included in a pixel and a transfer transistor configured to transfer an electrical signal generated by the photodiode; a first middle layer under the top layer and bonded to the top layer, wherein the first middle layer includes a plurality of capacitors connected to the transfer transistor through a first output node connected to the transfer transistor, and a plurality of sampling transistors connected to the plurality of capacitors and configured to control the plurality of capacitors; a second middle layer under the first middle layer and bonded to the first middle layer, wherein the second middle layer includes a source-follow transistor connected to the plurality of sampling transistors through a second output node; and a bottom layer under the second middle layer and bonded to the second middle layer, wherein the bottom layer includes an analog-to-digital converter (ADC) circuit configured to process a pixel signal output through the source-follow transistor.