Stacked Pixel Circuit Layout for Lower Parasitic Capacitance
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Solution Overview
Problem
In imaging devices with a three-dimensional structure, stacking three semiconductor layers can lead to increased chip size and hinder miniaturization due to electrical connections between the layers, and the connection via for the floating diffusion wire reduces the effective pixel circuit area, limiting the expansion of amplification transistors.
Innovation Solution
An imaging device design featuring a first substrate with a photodiode and floating diffusion, a second substrate with a pixel circuit, and a wire that electrically connects the floating diffusion to an amplification transistor, with a trench on the second substrate to reduce parasitic capacitance and improve charge-voltage conversion efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If three layers of semiconductor substrates are stacked to achieve three-dimensional structure, then pixel densification is improved, but chip size increases and miniaturization is hindered
Solution Approach 1:
The patent transitions from planar two-dimensional pixel arrangement to three-dimensional stacked structure by bonding multiple semiconductor substrates vertically. This dimensional change allows pixels to be arranged in multiple layers, significantly increasing pixel density without proportionally increasing chip area, thus resolving the contradiction between pixel densification and chip size miniaturization.
Solution Approach 2:
The imaging device is divided into multiple independent semiconductor substrates (first substrate with photodiodes, second substrate with pixel circuits, third substrate with signal processing circuits). Each substrate can be independently designed and manufactured, allowing optimization of each layer's function while maintaining overall compactness, thereby achieving high pixel density without excessive chip size increase.
2Reliability
If connection via is used to connect floating diffusion to amplification transistor, then electrical connection is achieved, but effective pixel circuit area is reduced
Solution Approach 1:
The patent applies different connection methods to different regions: in the pixel region, floating diffusion is connected to the amplification transistor gate through optimized via structures with minimal area occupation, while in peripheral regions, broader connection methods are used. This localized optimization maintains reliable electrical connection while minimizing the area consumed by connection structures in the critical pixel region.
Solution Approach 2:
The patent introduces intermediate connection structures (such as conductive plugs and optimized via designs) that serve as mediators between the floating diffusion and the amplification transistor gate. These intermediary structures reduce the direct area occupation while ensuring reliable electrical connection, effectively resolving the contradiction between connection reliability and area efficiency.
3Reliability
If wire penetrates both substrates to connect floating diffusion to amplification transistor, then electrical connection is achieved, but parasitic capacitance increases
Solution Approach 1:
The patent extracts the wire penetration path from passing through both substrates completely, and instead routes the wire to penetrate only the necessary substrate thickness or uses surface-level connections where possible. This extraction of the wire from the full penetration path reduces the length of conductive material, thereby reducing parasitic capacitance while maintaining the essential electrical connection between floating diffusion and amplification transistor.
Solution Approach 2:
The patent optimizes wire parameters including material composition, cross-sectional area, and routing path to minimize parasitic capacitance. By changing these parameters, the wire maintains sufficient electrical connection reliability while reducing capacitive effects that would otherwise degrade signal quality and increase energy loss.
Data Source
AI summary
An imaging device of an embodiment has a first substrate, a second substrate, a wire, and a trench. The first substrate has a pixel having a photodiode and a floating diffusion that holds a charge converted by the photodiode. The second substrate has a pixel circuit that reads a pixel signal based on the charge held in the floating diffusion in the pixel, and is stacked on the first substrate. The wire penetrates the first substrate and the second substrate in a stacking direction, and electrically connects the floating diffusion in the first substrate to an amplification transistor in the pixel circuit of the second substrate. The trench is formed at least in the second substrate, runs in parallel with the wire, and has a depth equal to or greater than the thickness of a semiconductor layer in the second substrate.