Stacked Pixel Transistor Layout for Short-Channel Noise Control
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Solution Overview
Problem
The miniaturization of pixels in solid-state imaging devices leads to a reduction in area for transistor placement, causing short channel effects and noise issues that affect the electrical properties of the transistor, necessitating a solution to improve transistor performance.
Innovation Solution
A solid-state imaging device is designed with a first semiconductor layer containing pixels and a second semiconductor layer stacked on the opposite side, where the first transistor is electrically coupled to the pixel and has a gate lengthwise direction inclined with respect to the pixel arrangement, allowing for increased gate length and improved electrical properties by preventing short-channel effects and noise.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of moving object
If pixels are miniaturized to increase pixel density, then pixel area is reduced, but the area available for transistor placement is reduced causing short channel effects and noise issues
Solution Approach 1:
The patent applies dimensionality change by stacking the pixel circuit on a separate substrate (second substrate) beneath the pixel substrate (first substrate). This vertical stacking approach moves the transistor placement problem from the two-dimensional pixel plane to a third-dimensional space, allowing sufficient transistor area to be secured without compromising pixel miniaturization. The pixel circuit is formed in the second substrate with transistors having channel lengths of 0.5 μm or more, preventing short channel effects while maintaining compact pixel dimensions.
Solution Approach 2:
The patent segments the imaging device into two separate functional substrates: the first substrate containing the pixels for light detection, and the second substrate containing the pixel circuits for signal processing. This segmentation allows each substrate to be optimized independently - the pixel substrate can be minimized for high density while the circuit substrate provides adequate space for transistors with sufficient channel length, thereby resolving the contradiction between pixel size and transistor performance.
2Length of moving object
If transistor gate length is increased to prevent short channel effects, then transistor area increases, but pixel area becomes insufficient for accommodating the transistor
Solution Approach 1:
The patent resolves this contradiction by transitioning to three-dimensional stacking architecture. The pixel circuit substrate is positioned beneath the pixel substrate, creating vertical separation. This allows transistors in the pixel circuit to have adequate gate lengths (0.5 μm or more) without consuming horizontal pixel area, as the transistors occupy space in the vertical dimension rather than competing for planar area with the pixels.
Solution Approach 2:
By segmenting the device into separate pixel and circuit substrates, the patent allows independent optimization of transistor gate length in the circuit substrate without constraining pixel area in the pixel substrate. The channel formation regions in the second substrate can extend sufficiently to provide adequate gate lengths while the first substrate maintains compact pixel dimensions for high density arrangement.
3Device complexity
If pixel circuit is integrated with pixels in the same substrate, then device complexity is reduced, but transistor electrical properties deteriorate due to insufficient area
Solution Approach 1:
The patent applies segmentation by dividing the device into two separate substrates: the first substrate for pixels and the second substrate for pixel circuits. This segmentation prioritizes transistor electrical properties over structural simplicity, allowing transistors to achieve adequate channel lengths (0.5 μm or more) and proper area for reliable operation. The separate substrate architecture enables independent optimization of circuit transistor dimensions without being constrained by pixel area limitations.
Solution Approach 2:
The patent uses vertical stacking in the third dimension to maintain relatively simple device structure while improving transistor properties. By placing the pixel circuit substrate beneath the pixel substrate, the design achieves sufficient transistor area and channel length control without requiring complex lateral arrangements. The vertical integration maintains compact form factor while enabling transistors to have adequate dimensions for reliable electrical performance.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration enables the miniaturization of pixels while enhancing the electrical properties of the transistor, specifically reducing Random Telegraph Signal noise and thermal noise, thereby improving the overall performance of the pixel circuit.
Implementation Method 1
The pixel includes a photoelectric converter
Data Source
AI summary
A solid-state imaging device is provided that enables miniaturization of a pixel and improvement in electrical properties of a transistor of a pixel circuit. The solid-state imaging device includes a first semiconductor layer and a second semiconductor layer. In the first semiconductor layer, a pixel including a photoelectric converter is arranged in a matrix along a plane direction. The number of the pixel is two or more. The second semiconductor layer is stacked on the first semiconductor layer on an opposite side to a light-incoming side of the pixel. In the second semiconductor layer, a first transistor electrically coupled to the pixel is provided. A gate lengthwise direction of the first transistor is inclined with respect to an arrangement direction of the pixel.