3D Stacked Pixel Via Layout for Lower Adjacent Pixel Interference
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Solution Overview
Problem
In imaging devices with a three-dimensional structure, the stacked arrangement of pixels makes it difficult to design the structure considering the position of vias that connect two semiconductor substrates, leading to increased capacitance with adjacent vertical signal lines and interference between pixels.
Innovation Solution
A light detection device is designed with a through-via that connects the first substrate portion with a pixel and the second substrate portion with a readout circuit, positioned between the contact portions of pixel transistors in a region of the pixel and shifted orthogonally to the direction of the contact portions, reducing the influence on adjacent pixels.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If pixels are arranged in a three-dimensional stacked structure to achieve higher pixel density, then pixel density is improved, but the design flexibility and control over via positions deteriorate
Solution Approach 1:
The patent transitions from a two-dimensional pixel arrangement to a three-dimensional stacked structure, utilizing the vertical dimension to increase pixel density. Multiple semiconductor substrates are stacked with through-vias connecting corresponding pixels across layers, enabling higher pixel density while maintaining design flexibility through careful via placement in the vertical dimension.
Solution Approach 2:
The pixel array is divided into multiple semiconductor substrates stacked in the vertical direction. Each substrate contains a portion of the pixel array and associated circuitry, with through-vias providing electrical connections between corresponding pixels in different substrates. This segmentation allows independent design and optimization of each layer while achieving high overall pixel density.
2Device complexity
If through-vias are positioned to connect stacked substrates, then three-dimensional structure is achieved, but capacitance with adjacent vertical signal lines increases
Solution Approach 1:
The patent positions through-vias at specific locations within each pixel region, optimizing their placement to minimize capacitance coupling with adjacent vertical signal lines. The via positions are carefully selected in the horizontal plane and vertical stacking to create local optimization of electrical isolation, reducing interference while maintaining the three-dimensional stacked structure.
3Area of stationary object
If pixel transistors are shared among multiple sensor pixels to reduce area, then area efficiency is improved, but the position of through-vias becomes more difficult to design
Solution Approach 1:
The patent implements shared pixel transistors where amplification and selection transistors are共用 among multiple sensor pixels (e.g., 2×2 pixels sharing transistors). This merging reduces the area required per pixel while the through-via positions are strategically designed to accommodate the shared transistor layout, connecting corresponding shared transistor regions across stacked substrates.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution reduces the influence of signal lines from adjacent pixels without lowering the photoelectric conversion efficiency, allowing for a more efficient and flexible design of the light detection device.
Implementation Method 1
a pixel configured to photoelectrically convert incident light
Data Source
AI summary
Provided is a light detection device which allows influence on adjacent pixels to be reduced. The light detection device includes a first substrate portion, a second substrate portion, and a through via. The first substrate portion has a pixel configured to photoelectrically convert incident light. The second substrate portion has a readout circuit configured to output a pixel signal based on charge output from the pixel to a signal line. The through via configured to connect the first substrate portion and the second substrate portion. The pixel has a floating diffusion configured to temporarily retain charge generated by photoelectric conversion. The readout circuit has a first pixel transistor connected to the floating diffusion through the through via and a second pixel transistor connected to the first pixel transistor and the signal line. The through via is provided, in plan view, in a direction orthogonal to a wiring path configured to connect between a contact portion of the first pixel transistor and a contact portion of the second pixel transistor in a region of the pixel.