Stacked Pixel Transistor Structure With Shared OLED Voltage Lines

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Solution Overview

Problem

Existing flat panel display devices, particularly OLED displays, face challenges in achieving high integration density and efficient power consumption while maintaining fast response speeds.

Innovation Solution

The display device incorporates a substrate with transistors and light-emitting elements connected through contact holes, sharing voltage lines between adjacent sub-pixels, and utilizing polycrystalline silicon and oxide semiconductor layers to enhance integration density and power efficiency.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Quantity of substance

If multiple separate voltage lines are used for each sub-pixel, then each sub-pixel can be independently controlled, but the integration density is reduced due to increased line occupancy

Engineering Contradiction:
Improveintegration densityVSAvoidvoltage line configuration
Core Design Contradiction:
Quantity of substanceVSDevice complexity

Solution Approach 1:

Adjacent sub-pixels share common voltage lines (ELVDD and ELVSS) instead of having separate voltage lines for each sub-pixel. This merging of voltage line resources increases integration density by reducing the total number of voltage lines required, while still maintaining independent control capability through shared transistor structures.

Inventive Principle:
Principle #5Merging (Combining)

Solution Approach 2:

The voltage lines are designed to serve multiple sub-pixels simultaneously, making them multi-functional. The same voltage line can be shared by multiple adjacent sub-pixels, reducing the overall line occupancy and improving integration density without sacrificing the ability to independently control each sub-pixel through its dedicated transistors.

Inventive Principle:
Principle #6Universality (Multi-functionality)

2Quantity of substance

If transistors are positioned vertically to save horizontal space, then integration density improves, but contact hole alignment and manufacturing precision become more challenging

Engineering Contradiction:
Improveintegration densityVSAvoidcontact hole alignment
Core Design Contradiction:
Quantity of substanceVSManufacturing precision

Solution Approach 1:

The transistor layout transitions from a horizontal arrangement to a vertical stacking configuration, utilizing the vertical dimension to improve integration density. The first and second transistors are positioned vertically with their active regions aligned in the vertical direction, allowing for more efficient use of substrate space while maintaining manufacturability through precise contact hole formation between layers.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This configuration improves integration density and power efficiency, allowing for high-quality image display with precise current control and reduced power consumption.

Implementation Method 1

organic light-emitting diodes, which emit light through the recombination of electrons and holes

Methodology Applied
Scientific EffectElectroluminescence: Electroluminescence

Data Source

PatentEP4712745A1Display device
Publication Date: 2026.03.18 SAMSUNG DISPLAY CO LTD
  • EP4712745A1 patent drawingFigure 1
  • EP4712745A1 patent drawingFigure 2
  • EP4712745A1 patent drawingFigure 3

AI summary

Provided is a display device (10) including a substrate (100), a first transistor (T1) positioned on the substrate (100) and including a first semiconductor layer (510) and a first gate electrode (520), a second transistor (T2) positioned on the first transistor (T1) and including a second semiconductor layer (550) and a second gate electrode (571), and a light-emitting element (400) positioned on the second transistor (T2) and electrically connected to the first transistor (T1), wherein the first gate electrode (520) of the first transistor (T1) and the second semiconductor layer (550) of the second transistor (T2) are electrically connected through a contact hole.