Stacked Pixel Circuit Layout With Variable Interchip Wiring Paths
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Solution Overview
Problem
Current semiconductor apparatuses face limitations in performance and quality due to insufficient examination of multi-layer wiring connections between stacked substrates, leading to increased time and cost in the design and manufacturing phases.
Innovation Solution
A semiconductor apparatus is designed with a stack of two chips, where the first chip has a matrix of pixel circuits and the second chip has a matrix of electric circuits, with specific wiring structures and conductive portions to optimize electrical connections, allowing for varying lengths of wiring paths to enhance layout flexibility and reduce design complexities.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If multi-layer wiring is used for connection between substrates, then electrical connectivity is achieved, but design complexity and manufacturing difficulty increase
Solution Approach 1:
The patent transitions from planar wiring to three-dimensional stacked substrate architecture, allowing wiring paths to extend in the vertical dimension (through-substrate vias, inter-substrate connections) rather than being confined to two-dimensional layers. This dimensional change enables more efficient routing and reduces wiring congestion while maintaining electrical connectivity.
Solution Approach 2:
The patent divides the semiconductor device into multiple independent substrate layers (first substrate with pixel circuits, second substrate with signal processing circuits, third substrate with memory circuits). Each substrate can be designed and manufactured separately, then stacked and connected, thereby reducing the complexity of designing a single monolithic substrate with all functions.
2Reliability
If multi-layer wiring is used for connection between substrates, then electrical connectivity is achieved, but manufacturing time and cost increase
Solution Approach 1:
The patent employs preliminary substrate preparation where each substrate is fully fabricated, tested, and prepared with its wiring structures before stacking. This allows parallel manufacturing of multiple substrates simultaneously, reducing overall manufacturing time compared to sequential assembly. The connection structures (bumps, vias) are pre-formed on each substrate prior to bonding.
Solution Approach 2:
The patent introduces intermediary connection structures (such as bump electrodes, through-substrate vias, and adhesive layers with conductive patterns) that facilitate reliable electrical connections between substrates. These intermediaries simplify the bonding process and enable automated manufacturing, reducing both time and cost.
3Adaptability or versatility
If wiring paths are made longer to connect circuits, then layout flexibility increases, but signal transmission delay increases
Solution Approach 1:
The patent utilizes the vertical dimension in stacked substrates to create direct, short wiring paths between corresponding circuits on different substrates. Through-substrate vias and inter-substrate connection structures provide direct vertical pathways, minimizing horizontal wiring length and reducing signal delay while enabling flexible circuit placement on each substrate layer.
Data Source
AI summary
A semiconductor apparatus includes a stack of a first chip having a plurality of pixel circuits arranged in a matrix form and a second chip having a plurality of electric circuit arranged in a matrix form. A wiring path between a semiconductor element configuring the pixel circuit and a semiconductor element configuring the electric circuit or a positional relationship between a semiconductor element configuring the pixel circuit and a semiconductor element configuring the electric circuit is differentiated among the electric circuits.