Stacked Pixel Wiring Layout for Low-Noise Solid-State Imaging
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Solution Overview
Problem
Existing solid-state imaging devices face challenges in suppressing noise due to increased parasitic capacitance, reduced aperture ratio, and interference between readout wire lines, especially in miniaturized designs.
Innovation Solution
The proposed imaging device incorporates a first chip with a specific wiring layer configuration, including anode and cathode electrodes, vias, and shield wiring, which are strategically arranged to minimize parasitic capacitance and interference, thereby enhancing noise suppression.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If the avalanche photodiode and quench circuit are laminated to increase aperture ratio, then the aperture ratio is improved, but the distance between cathode wire line and electrode is shortened, increasing parasitic capacitance and noise
Solution Approach 1:
The patent transitions from a planar arrangement to a three-dimensional stacked configuration, placing the quench circuit on a separate chip (mount substrate) beneath the photodiode chip. This vertical stacking allows the aperture ratio to be maximized in the horizontal plane while maintaining adequate distance between cathode wire lines and electrodes in the vertical dimension, thereby reducing parasitic capacitance.
2Manufacturing precision
If pixel size is decreased to increase the number of pixels, then the resolution is improved, but the quench circuit must be arranged outside the active region, decreasing the aperture ratio
Solution Approach 1:
The patent divides the imaging device into separate functional modules: a photodiode chip containing only the light-sensitive pixel array with high aperture ratio, and a separate mount substrate containing the quench circuits. This segmentation allows each module to be optimized independently - the photodiode chip achieves maximum aperture ratio by eliminating circuit elements from the pixel area, while the quench circuits are consolidated on the mount substrate.
3Object-affected harmful factors
If readout wire line width is increased to reduce interference, then the signal quality is improved, but the distance from reference plane must be increased, reducing design freedom
Solution Approach 1:
The patent extracts the readout wire lines and quench circuits from the photodiode chip and relocates them to a separate mount substrate. This extraction eliminates the constraint of maintaining large distances between wire lines on the same chip, allowing compact pixel design while providing sufficient spacing for low-interference readout wiring on the dedicated mount substrate.
Data Source
AI summary
An imaging device includes a first chip. The first chip includes a first pixel and a second pixel. The first pixel includes a first anode region and a first cathode region, and the second pixel includes a second anode region and a second cathode region. The first chip includes a first wiring layer. The first wiring layer includes a first anode electrode, a first anode via coupled to the first anode electrode and the first anode region, and a second anode via coupled to the first anode electrode and the second anode region.