Stacked PMOS Voltage Tracking Circuit for Compact ESD Protection
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Solution Overview
Problem
The miniaturization of integrated circuits has increased their susceptibility to electrostatic discharge (ESD) events due to thinner dielectric thicknesses and lowered dielectric breakdown voltages, leading to potential electronic circuit damage.
Innovation Solution
A voltage tracking circuit is implemented with PMOS transistors positioned in separate wells, creating a stacked structure that enhances ESD immunity and occupies less area by utilizing parasitic diodes and transistors in different wells to divert ESD current effectively.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by moving object
If integrated circuits are miniaturized to consume less power and provide more functionality, then power consumption decreases and functionality increases, but susceptibility to electrostatic discharge (ESD) events increases due to thinner dielectric thicknesses and lowered dielectric breakdown voltages
Solution Approach 1:
The patent utilizes the parasitic diodes and transistors that naturally exist in the stacked transistor structure to divert ESD current. Instead of viewing these parasitic elements as unwanted byproducts that reduce reliability, the invention intentionally designs the circuit to exploit them for ESD protection, converting a harmful factor into a beneficial protective mechanism
Solution Approach 2:
The stacked transistor structure acts as an intermediary mechanism between the ESD event and the sensitive circuit nodes. The parasitic diodes and transistors in the stacked structure serve as intermediate pathways that redirect ESD current away from critical components, providing protection without requiring additional dedicated protection circuits
2Reliability
If traditional ESD protection circuits are added to protect against electrostatic discharge, then ESD immunity improves, but circuit area increases significantly
Solution Approach 1:
The stacked transistor structure performs multiple functions simultaneously: it provides voltage tracking for normal circuit operation and ESD protection during electrostatic discharge events. By making the same structural elements serve dual purposes, the invention avoids adding dedicated protection circuits that would increase area
Solution Approach 2:
The patent merges the voltage tracking function and ESD protection function into a single integrated structure. The same stacked transistors and parasitic elements that enable voltage tracking also provide the ESD current diversion path, combining what would traditionally be separate functional blocks into one compact unit
3Volume of moving object
If dielectric thickness is reduced to enable miniaturization, then device size decreases, but dielectric breakdown voltage decreases leading to increased ESD susceptibility
Solution Approach 1:
The patent transitions from protecting against ESD in the vertical dimension (through thicker dielectrics) to protecting through lateral current diversion pathways. By creating alternative current paths that bypass the thin dielectric regions, the invention provides ESD protection without requiring increased dielectric thickness in the vertical dimension
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution provides improved ESD immunity and reduces the circuit area, effectively managing ESD events without significant space increase.
Implementation Method 1
utilizing parasitic diodes and transistors in different wells to divert ESD current effectively
Implementation Method 2
The miniaturization process has also increased the devices' susceptibility to electrostatic discharge (ESD) events
Data Source
AI summary
A voltage tracking circuit includes a first, second, third and fourth transistor. The first transistor is in a first well. The first transistor includes first source terminal coupled to a first voltage supply. The second transistor includes a second source terminal coupled to the first drain terminal, and a second gate terminal coupled to a pad voltage terminal. The third and fourth transistor are in a second well. The third transistor includes a third source terminal and a third gate terminal coupled to the first voltage supply. The fourth transistor includes a fourth drain terminal coupled to the third source terminal, a fourth gate terminal coupled to the third gate terminal and the first voltage supply, and a fourth source terminal being coupled to the pad voltage terminal.