Stacked Polysilicon ESD Protection for Semiconductor Devices
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Solution Overview
Problem
Conventional semiconductor devices face challenges in increasing the junction area of bidirectional Zener diodes and reducing internal resistance of electrostatic discharge protection elements, which limits their tolerance to static electricity, especially in restricted chip plane regions.
Innovation Solution
The semiconductor device employs a heterojunction field effect transistor configuration where the electrostatic protection passive element is formed by overlapping two layers of semiconductor regions, allowing for a larger junction area and reduced internal resistance without increasing manufacturing steps.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the junction area of the bidirectional Zener diode is increased to improve electrostatic tolerance, then the tolerance to static electricity is enhanced, but the chip area required increases which is not feasible in restricted chip plane regions
Solution Approach 1:
The patent transitions from a planar single-layer structure to a three-dimensional multi-layer stacked structure. The electrostatic protection passive element is formed by stacking first and second semiconductor layers vertically, with conductive types alternating between layers. This vertical stacking in the third dimension increases the junction area without expanding the chip footprint, resolving the contradiction between electrostatic tolerance and chip area.
2Reliability
If the internal resistance of the electrostatic discharge protection element is reduced to improve electrostatic tolerance, then the tolerance to static electricity is enhanced, but the device complexity increases
Solution Approach 1:
The patent combines multiple functions into a single integrated structure. The stacked semiconductor layers form both the bidirectional Zener diode for electrostatic discharge protection and the protection resistor in one unified passive element. This merging reduces device complexity by eliminating separate components while simultaneously achieving low internal resistance through the multi-layer configuration that provides multiple parallel discharge paths.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration enhances the semiconductor device's tolerance to static electricity by increasing the junction area of the bidirectional Zener diode and the resistance value of the protection resistor, providing improved electrostatic protection without increasing manufacturing complexity or cost.
Implementation Method 1
the static electricity is discharged from the external gate electrode terminal to a source electrode at a ground potential through a bidirectional Zener diode provided as the mechanism for discharging the static electricity
Implementation Method 2
a part of the static electricity applied to the external gate electrode terminal enters the gate electrode through the resistor for the protection from the static electricity, and is then diffused into the inside of the gate electrode
Data Source
AI summary
An electrostatic discharge protection element and a protection resistor, which are formed on an N− drain region with a field oxide film interposed therebetween for the purpose of preventing electrical breakdown of a field effect transistor, are composed as a stacked bidirectional Zener diode of one or a plurality of N+ polycrystalline silicon regions of a first layer and a P+ polycrystalline silicon region of a second layer, and a stacked resistor of one or a plurality of N+ resistor layers of the first layer and an N+ resistor layer of the second layer, respectively. One end of the plurality of N+ polycrystalline silicon regions of the first layer is connected to an external gate electrode terminal, and the other end is connected to a source electrode. One end of the plurality of N+ resistor layers of the first layer is connected to a gate electrode, and the other end is connected to the external gate electrode terminal. Semiconductor regions of the first layer and the second layer are formed by using semiconductor films, which form a hetero semiconductor region and the gate electrode, respectively.