3D Stacked Polysilicon Resistance and Capacitance Elements
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
In semiconductor integrated circuits with 3-dimensional stacked layer structures, the formation of effective resistance and capacitance elements is hindered by the lack of sufficient study on the connection relationships of conductive layers, particularly in BiCS memory where contact plugs are not disposed between layers, necessitating innovative techniques for 3-dimensional formation.
Innovation Solution
The conductive layers, made of polysilicon, are stacked with stairstep ends and connected in series by metal layers to form resistance and capacitance elements, allowing for 3-dimensional formation and integration within the semiconductor device.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If contact plugs are not disposed between conductive layers (as in BiCS memory), then manufacturing process is simplified, but connection between conductive layers becomes difficult
Solution Approach 1:
The patent transitions from 2D planar connections to 3D stacked connections by forming conductive layers in multiple stacked configurations. The first and second conductive layers are positioned at different heights and connected through vertical vias, enabling three-dimensional integration without requiring traditional contact plugs between each layer.
Solution Approach 2:
The patent merges the connection function of multiple conductive layers into a unified three-dimensional structure. The first conductive layer, second conductive layer, and their interconnections form an integrated network that performs multiple electrical connection functions simultaneously, eliminating the need for separate contact plug structures.
2Productivity
If 3-dimensional stacked layer structure is used, then integration density is improved, but formation of resistance and capacitance elements becomes difficult
Solution Approach 1:
The conductive layers serve multiple functions simultaneously: they act as interconnect wiring for signal transmission and as electrode structures for forming resistance and capacitance elements. The same stacked conductive layer configuration provides both electrical connection and passive element formation capabilities.
Solution Approach 2:
The patent segments the conductive layers into functionally distinct regions. The first conductive layer forms one electrode of the capacitance element, the second conductive layer forms the other electrode, while additional segments create resistance elements through specific geometric configurations and material properties.
3Ease of manufacture
If conventional 2D structure is used, then element formation is easy, but area occupied by resistance and capacitance elements is large
Solution Approach 1:
The patent moves passive element formation from the 2D plane to the 3D vertical dimension. Resistance and capacitance elements are formed within the stacked conductive layer structure, utilizing the vertical space between layers rather than occupying additional horizontal area.
Solution Approach 2:
The patent nests resistance and capacitance elements within the conductive layer stack structure. The passive elements are embedded in the interconnection architecture itself, with electrodes and resistive/capacitive regions integrated into the same vertical columnar structure.
Data Source
AI summary
A semiconductor device is comprised of a semiconductor substrate, conductive layers stacked above the semiconductor substrate, which is comprised of a conductive polysilicon, and a metal layer provided above the conductive layers. Both ends of the conductive layers have stairsteps respectively. The conductive layers are connected in series by a metal layer which is provided on the stairsteps. The conductive layers connected in series comprise a resistance element.