Stacked Polysilicon Resistor Structure for Stable Resistance Control
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Solution Overview
Problem
Existing semiconductor devices face challenges in adjusting resistance values without changing chip size and minimizing resistance variations, particularly when increasing resistance values, as reducing the width of resistive elements leads to increased variations.
Innovation Solution
A semiconductor device configuration featuring stacked resistance layers with higher impurity concentration contact parts, allowing for adjustment of resistance values without altering chip size, achieved through specific layer thickness, length, and impurity concentration adjustments, and ohmic contact optimization.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If the width of the resistor is decreased to increase the resistance value without changing chip size, then the resistance value is increased, but the variation in resistance value is increased
Solution Approach 1:
The patent transitions from a single-layer resistor structure to a multi-layer stacked structure, adding the vertical dimension (stacking direction) to the design. Multiple resistance layers are stacked in the height direction and connected via contact holes, allowing resistance value adjustment through the number of layers while maintaining sufficient in-plane dimensions to minimize variation.
Solution Approach 2:
The patent employs multiple parameters to control resistance value: the number of stacked layers, the thickness of each resistance layer, the impurity concentration in the polysilicon, and the contact hole dimensions. By adjusting these parameters, the desired resistance value is achieved without reducing the width of individual layers, thereby maintaining low variation.
2Manufacturing precision
If the chip size of the resistive element is increased to increase the resistance value, then the resistance value is increased, but the packaging area must be changed for each semiconductor module
Solution Approach 1:
The patent utilizes the vertical stacking direction to increase resistance value without expanding the horizontal chip footprint. By stacking multiple resistance layers in the height direction, the resistance value can be adjusted while maintaining a consistent chip size that fits standard packaging requirements across different semiconductor modules.
Solution Approach 2:
The total resistance is segmented into multiple discrete resistance layers stacked vertically. Each layer contributes to the overall resistance value, allowing flexible adjustment of the total resistance by changing the number of layers or their individual properties, while the horizontal dimensions remain constant for standardized packaging.
3Reliability
If higher impurity concentration is used in contact parts, then ohmic contact is improved, but the resistance value control becomes more complex
Solution Approach 1:
The patent applies different impurity concentrations to different regions of the resistance layers. The contact parts (regions contacting the electrodes or interlayer connections) have higher impurity concentration to ensure low contact resistance and good ohmic contact, while the main body parts have lower impurity concentration to provide the desired resistance value. This localized differentiation optimizes both contact quality and resistance control.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration enables precise control of resistance values, reduces variations, and prevents damage to the resistive elements during bonding, while maintaining a stable resistance across temperature changes.
Implementation Method 1
a first contact part having a higher impurity concentration than the body part, and the respective first contact parts of the first resistance layer and the second resistance layer are in contact with each other via a contact hole
Data Source
AI summary
A semiconductor device includes: a semiconductor substrate; a first insulating film provided on one surface of the semiconductor substrate; a first resistance layer including polysilicon provided on the first insulating film; a second insulating film provided on the first resistance layer; a second resistance layer including polysilicon provided on the second insulating film so as to overlap with the first resistance layer; a third insulating film provided on the second resistance layer; a first electrode provided over the third insulating film and electrically connected to the second resistance layer; and a second electrode electrically connected to the first resistance layer, wherein the first resistance layer and the second resistance layer each include a body part and a first contact part having a higher impurity concentration than the body part, and the respective first contact parts are in contact with each other.