3D Stacked Potential Sensor Layout for Low-Noise Fast Sampling
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Solution Overview
Problem
Existing potential measurement devices face challenges in achieving high resolution and high sampling rates due to long-distance wiring between amplifier and AD conversion circuits, leading to increased noise and variation in offset, which deteriorate the sampling rate and accuracy.
Innovation Solution
A potential measurement device with a stacked configuration of a first substrate having a two-dimensional electrode array and a second substrate with a corresponding two-dimensional AD conversion circuit array, minimizing wiring length and equalizing wiring lengths across all cells to reduce noise and offset variation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Object-affected harmful factors
If the read circuit/reference circuit, load PMOS, current source NMOS, and A/D conversion circuit are physically separated from each other, then noise reduction and signal isolation are improved, but wiring length increases leading to increased wiring resistance and capacitance
Solution Approach 1:
The patent transitions from a planar layout to a three-dimensional stacked configuration, placing the electrode array on one substrate and the AD conversion circuits on another substrate positioned directly beneath it. This vertical arrangement dramatically reduces wiring length while maintaining circuit isolation, effectively resolving the contradiction between noise reduction and wiring length reduction.
2Measurement precision
If electrodes are densely spread to achieve high resolution, then measurement precision is improved, but wiring capacitance increases leading to deterioration in sampling rate
Solution Approach 1:
By stacking the AD conversion circuits directly beneath the electrode array in three dimensions, the patent minimizes the horizontal wiring distance required to connect each electrode to its corresponding converter. This dramatically reduces wiring capacitance even when electrodes are densely packed, thereby maintaining high sampling rates while achieving high spatial resolution.
3Measurement precision
If wiring length between amplifier and AD conversion circuits is reduced, then noise and offset variation are reduced, but device complexity increases due to stacked configuration
Solution Approach 1:
The patent divides the device into functionally independent substrates: one containing the electrode array and amplifier circuits, and another containing the AD conversion circuits. This segmentation allows each substrate to be optimized independently while the vertical interconnection minimizes wiring length, achieving low offset variation with manageable complexity through modular design.
Data Source
AI summary
Provided is a potential measurement device including: a first substrate having read electrodes arranged in a two-dimensional array; and a second substrate on which the first substrate is stacked, in which each of the read electrodes includes at least one or more AD conversion circuits each having independent correspondence to the read electrode, and at least a part of the AD conversion circuits is arranged in a two-dimensional array on the second substrate.