Semiconductor Package Structure With Stacked Power Chips and Lead-Free Bonding
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Solution Overview
Problem
The existing Quad Flat No-Lead (QFN) semiconductor package structure faces limitations in reducing package height, uses lead-containing solder paste causing environmental and health concerns, and experiences accuracy issues due to high-temperature reflow processes.
Innovation Solution
A semiconductor package structure integrating a control chip and power chips within a single package using dielectric and conductive layers, conductive adhesive parts, and connecting elements, replacing the conventional lead frame and solder paste with a semiconductor process to enhance electrical performance and reduce volume, while eliminating lead-containing manufacturing processes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If lead-containing solder paste is used to join components, then manufacturing process is simple, but environmental pollution and health impact increase
Solution Approach 1:
The patent changes the material composition parameter by replacing lead-containing solder paste with lead-free solder paste, maintaining the joining function while eliminating harmful environmental and health effects. This parameter change resolves the contradiction between manufacturing simplicity and environmental protection.
2Strength
If high temperature reflow process is used to join components, then components are firmly fixed, but component displacement occurs before all components are fixed reducing accuracy
Solution Approach 1:
The patent applies preliminary action by pre-heating the substrate to a temperature close to the solder melting point before placing components, then using a lower temperature reflow process. This preliminary heating ensures uniform temperature distribution across the substrate, preventing component displacement during the joining process while achieving strong joints.
3Power
If copper sheet and lead frame are used in QFN package structure, then high power requirements are met, but package height cannot be reduced
Solution Approach 1:
The patent transitions from a traditional planar lead frame structure to a three-dimensional stacked chip structure. By stacking multiple chip layers vertically and using through-substrate vias for electrical connections, the design achieves high power capability in a reduced horizontal footprint while minimizing package height, effectively resolving the contradiction between power handling and package size.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution reduces package volume, improves electrical performance, and addresses environmental concerns by eliminating lead usage and enhancing manufacturing accuracy through the semiconductor process, resulting in a more efficient and environmentally friendly packaging method.
Implementation Method 1
a first conductive adhesive part electrically connecting the second electrode layout of the first power chip to the first patterned conductive layer
Data Source
AI summary
The present invention provides a semiconductor package structure including a first dielectric layer, an integrated chip, a second power chip, a first patterned conductive layer, a second patterned conductive layer, a first conductive adhesive part, a second conductive adhesive part, a plurality of first conductive connecting elements and a plurality of second conductive connecting elements, and including a build-up circuit structure below, wherein the integrated chip includes a control chip and a first power chip. By means of integrating the control chip and the first power chip into a single chip, volume of semiconductor package structure can be further reduced. In addition, a manufacturing method of a semiconductor package structure is also provided.