Stacked Power Semiconductor Chips with Diffusion Soldering
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Solution Overview
Problem
Existing technologies face challenges in efficiently stacking and coupling power semiconductor chips for high-power applications, such as half-bridge circuits, which require precise electrical and thermal management, and existing manufacturing methods do not adequately address the need for reliable high-temperature and high-frequency operations.
Innovation Solution
The solution involves arranging two power semiconductor chips one above the other, with specific contact pads and metal layers for electrical and mechanical coupling, using diffusion soldering or conductive adhesives, and encapsulating with lamination foils to form a stable intermetallic phase, allowing for high-temperature and high-frequency operation while enabling efficient heat dissipation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Power
If power semiconductor chips are stacked one above another for high-power applications, then power handling capability and integration density are improved, but manufacturing complexity and coupling reliability become worse
Solution Approach 1:
The patent divides the power semiconductor device into multiple separate chips (first power semiconductor chip and second power semiconductor chip) that can be manufactured independently using standard processes, then stacked and coupled together. This segmentation allows each chip to be optimized separately while simplifying the overall manufacturing complexity.
Solution Approach 2:
The patent implements a vertical stacking configuration where one power semiconductor chip is positioned directly above another, creating a nested three-dimensional structure. This nesting approach increases power handling capability and integration density without requiring larger planar areas, while the standardized coupling interfaces help manage manufacturing complexity.
2Power
If power semiconductor chips are stacked one above another for high-power applications, then power handling capability is improved, but thermal management and electrical coupling reliability become worse
Solution Approach 1:
The patent incorporates preliminary thermal management structures and electrical coupling configurations during the chip design and manufacturing stages. Thermal pathways are pre-established through the stacked structure, and electrical contacts are pre-configured on chip surfaces to ensure reliable coupling when stacked, addressing thermal and reliability concerns before the stacking process occurs.
Solution Approach 2:
The patent employs composite material structures in the coupling layers and thermal interfaces between stacked chips. These composite materials combine electrical conductivity, thermal conductivity, and mechanical stability properties to simultaneously improve coupling reliability and thermal management in the high-power stacked configuration.
3Reliability
If diffusion soldering or conductive adhesives are used for coupling chips, then electrical and mechanical coupling is improved, but manufacturing process complexity increases
Solution Approach 1:
The patent uses diffusion soldering layers and conductive adhesive materials as intermediary substances between the stacked power semiconductor chips. These intermediaries provide both electrical conductivity and mechanical bonding, achieving reliable electrical and mechanical coupling while the standardized application processes help manage manufacturing complexity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration enables reliable high-power switching and control with improved heat transfer and mechanical stability, suitable for applications like DC-DC converters and motor controllers, enhancing the performance and reliability of power semiconductor devices.
Implementation Method 1
using diffusion soldering or conductive adhesives, and encapsulating with lamination foils to form a stable intermetallic phase
Implementation Method 2
allowing for high-temperature and high-frequency operation while enabling efficient heat dissipation
Data Source
AI summary
A device includes a first power semiconductor chip with a first contact pad and a second contact pad on a first face and a third contact pad on the second face. The device further includes a second power semiconductor chip with a first contact pad and a second contact pad on a first face and a third contact pad on the second face. The first and second power semiconductor chips are arranged one above another, and the first face of the first power semiconductor chip faces in the direction of the first face of the second power semiconductor chip. In addition, the first power semiconductor chip is located laterally at least partially outside of the outline of the second power semiconductor chip.