Stacked Power Line Structure for Semiconductor Device
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Solution Overview
Problem
The increasing density of semiconductor devices reduces the cross-section area of power lines, leading to decreased current capacity and potential operation stability issues due to reduced current flow.
Innovation Solution
A semiconductor device with a stacked power line structure, where a second power line is stacked on a first power line, increasing the cross-sectional area and reducing resistance, while maintaining a planar layout to avoid compromising signal line area.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the line width of power lines is reduced to increase device density, then the device density increases, but the current capacity decreases
Solution Approach 1:
The patent transitions from a single-layer power line structure to a multi-layer stacked structure, utilizing the vertical dimension to increase the effective cross-sectional area. This allows the power line to maintain sufficient current capacity while occupying less horizontal space, thereby supporting higher device density without compromising power delivery capability.
2Productivity
If the cross-section area of power lines is reduced, then the device density increases, but the operation stability deteriorates
Solution Approach 1:
By stacking multiple power line layers vertically, the invention maintains sufficient total cross-sectional area for stable operation while reducing the horizontal footprint. This enables higher device density without compromising the electrical stability and current carrying capacity required for reliable operation.
3Reliability
If the power line cross-section area is increased, then the current capacity increases, but the signal line area is compromised
Solution Approach 1:
The stacked power line structure utilizes the vertical dimension to provide increased current capacity through larger effective cross-sectional area, while maintaining a compact horizontal footprint. This allows signal lines to occupy the horizontal plane without interference, resolving the conflict between power delivery requirements and signal routing space.
Data Source
AI summary
A semiconductor device includes a substrate, a plurality of signal lines, and at least one power line. The substrate includes an integrated circuit unit. The signal lines are disposed on the substrate and are configured to provide the integrated circuit unit with signals. The power line is disposed on the substrate and is configured to provide the integrated circuit unit with power supply on the substrate. The power line includes a stacked structure including a first power line and a second power line stacked on the first power line.