Stacked Power-Line Layout for Narrow-Bezel Display Panels
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Solution Overview
Problem
Current display devices have a significant non-display region, known as the bezel, which reduces the effective display area and affects image quality due to the placement of power and data lines, making it challenging to minimize the bezel while maintaining image quality.
Innovation Solution
The display device is designed with a substrate that includes multiple display regions and a non-display region, where power lines and fan-out lines are strategically arranged with insulating layers to minimize the bezel area, allowing for a more efficient distribution of power and data signals to pixels, thereby reducing the non-display region and improving image quality.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If power lines and data lines are placed in the non-display region (bezel), then the display area can be maximized, but the bezel area increases and image quality deteriorates
Solution Approach 1:
The patent transitions from planar line routing to three-dimensional stacked routing. Power lines and data lines are arranged in multiple layers (first power line layer, second power line layer, data line layer) separated by insulating layers, allowing simultaneous minimization of bezel area and maintenance of signal integrity through vertical stacking rather than horizontal spreading.
Solution Approach 2:
The patent implements nested routing where data lines are positioned between first and second power lines in the vertical stack. The insulating layers are nested between conductive layers, creating a compact layered structure that fits all necessary signal paths within a minimized bezel region while maintaining electrical isolation.
2Area of stationary object
If the bezel area is minimized, then the display area increases, but uniform power supply and data signal distribution to pixels becomes difficult
Solution Approach 1:
By routing power and data lines through multiple vertical layers rather than spreading them horizontally, the patent achieves compact bezel area while maintaining adequate spacing and isolation between signal paths. This three-dimensional arrangement allows uniform distribution of power and data signals to pixels across the display area without requiring excessive bezel space.
Solution Approach 2:
Insulating layers serve as intermediaries between power lines and data lines, ensuring electrical isolation while allowing close proximity routing. This enables compact layered structure with minimized bezel area while maintaining signal integrity and uniform power supply to all pixels through proper insulation and spacing.
3Area of stationary object
If power lines and data lines are closely routed to minimize bezel, then manufacturing complexity increases due to multiple insulating layers
Solution Approach 1:
The patent segments the line routing into distinct horizontal layers (first power line layer, second power line layer, data line layer) separated by insulating layers. This segmentation simplifies manufacturing by allowing each layer to be processed independently with standard thin-film deposition techniques, reducing overall complexity despite the multi-layer structure.
Solution Approach 2:
The layered structure serves multiple functions simultaneously: it minimizes bezel area, provides electrical isolation between power and data lines, enables uniform signal distribution, and facilitates manufacturing through standardized layer-by-layer fabrication processes. This multi-functionality reduces overall system complexity despite the increased structural detail.
Data Source
AI summary
A display device includes a substrate including a first display region, a second display region having an area smaller than that of the first display region, a third display region having an area smaller than that of the first display region, and a non-display region, a plurality of pixels provided in the first to third display regions, a power line which is connected to each of the plurality of pixels and applies a first power voltage to the plurality of pixels, and a fan-out line provided in the non-display region, the fan-out line applying a data signal to the plurality of pixels, where the power line includes an additional power line, a first power line, and disposed on the additional power line, and a second power line disposed on the first power line.