Stacked Power Semiconductor Package for Compact Heat Dissipation
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Solution Overview
Problem
Existing semiconductor devices are large due to the arrangement of multiple power semiconductor chips and lack efficient heat dissipation and miniaturization strategies.
Innovation Solution
A semiconductor device configuration involving two substrates with semiconductor elements mounted with drains and sources down, a connection conductor for electrical connection between the elements, and a sealing part that covers the semiconductor elements but not the substrate surfaces, allowing for reduced size and improved heat dissipation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Volume of moving object
If multiple power semiconductor chips are connected and sealed in a conventional configuration, then the device provides necessary electrical connections and protection, but the device size becomes large
Solution Approach 1:
The patent transitions from a planar arrangement of multiple power semiconductor chips to a three-dimensional stacked configuration. The first and second power semiconductor chips are arranged in different planes (first and second directions respectively), utilizing vertical stacking to reduce the horizontal footprint. This dimensional change allows multiple chips to coexist in a compact volume without increasing device size proportionally.
Solution Approach 2:
The patent implements a nested arrangement where the first power semiconductor chip is positioned within the projection area of the second power semiconductor chip, and vice versa. The chips are arranged such that they overlap in the plan view, with one chip nested within the boundary of the other, maximizing space utilization and reducing overall device footprint.
2Temperature
If multiple power semiconductor chips are connected in a conventional configuration, then electrical connections are established, but heat dissipation becomes inefficient
Solution Approach 1:
The patent assigns different functional roles to different regions of the device. The first power semiconductor chip handles first current in a first direction, while the second power semiconductor chip handles second current in a second direction. This local functional differentiation allows optimized current paths and heat generation zones, improving overall heat dissipation efficiency by managing thermal loads from different chips separately.
Solution Approach 2:
By stacking chips in three dimensions rather than arranging them in a single plane, the patent creates separate thermal zones for each chip. The first chip generates heat in one region while the second chip generates heat in another region, allowing more effective thermal management and dissipation pathways without thermal interference between chips.
3Volume of moving object
If the sealing part covers all substrate surfaces, then complete protection is provided, but the device size cannot be reduced
Solution Approach 1:
The patent extracts the sealing function from covering the entire substrate area and applies it only to the necessary regions. The sealing part is positioned to cover specific areas where protection is needed (such as around the semiconductor chips and connection conductors) while leaving other substrate surfaces exposed. This selective sealing reduces the overall sealed volume and device size while maintaining adequate protection for critical components.
Data Source
AI summary
A semiconductor device includes a first substrate, a second substrate, a first semiconductor element, a second semiconductor element, a connection conductor, a connection conductor, and a sealing part. The first substrate includes a first surface, a second surface, a first insulating substrate, and a first conductive layer. The second substrate includes a third surface, a fourth surface, a second insulating substrate, and a second conductive layer. The first semiconductor element includes a first semiconductor layer, a first electrode, a second electrode, and a first control electrode. The second semiconductor element includes a second semiconductor layer, a third electrode, a fourth electrode, and a second control electrode. The connection conductor electrically connects the first and fourth electrodes. The sealing part covers a portion of the first substrate, a portion of the second substrate, the first semiconductor element, and the second semiconductor element.