Stacked Power Device Package with Die Attach Paddle
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Solution Overview
Problem
Conventional power device packages with multiple semiconductor chips have increased footprint and volume, leading to reliability issues and high manufacturing costs due to complex wiring processes, especially when using lower surfaces as electrodes.
Innovation Solution
A power device package design featuring a substrate with stacked power semiconductor chips and die attach paddles, including an adhesive layer and conductive patterns for simplified electrical connections, allowing the lower surface of the second power semiconductor chip to function as an electrode, and using a singulation process for cost-effective manufacturing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If multiple semiconductor chips are individually mounted in die attach regions of a substrate, then each chip can be electrically connected, but the footprint area and volume of the package increase
Solution Approach 1:
The patent transitions from a planar arrangement of multiple chips on a substrate to a vertical stacked configuration. The lower surface of each power semiconductor chip is used as an electrode, allowing chips to be stacked in the vertical dimension rather than spread out in the horizontal plane. This dimensional change reduces the package footprint area while maintaining electrical connection reliability through the die attach paddle structure.
Solution Approach 2:
The lower surface of the power semiconductor chip serves dual functions: as the active device surface and as an electrode for electrical connection. The die attach paddle also serves multiple functions: mechanical support, electrical connection, and thermal management. This multi-functionality enables compact stacking without compromising electrical reliability.
2Area of stationary object
If the footprint area and volume are reduced by stacking chips, then compactness is achieved, but the wiring process becomes complicated and expensive
Solution Approach 1:
The patent extracts the wiring complexity from the chip interconnection process by using the lower surface of each chip as a direct electrode. This eliminates the need for complex wire bonding or through-silicon via routing between stacked chips. The electrical connection is achieved through the die attach paddle that directly contacts the lower surface electrode, simplifying the manufacturing process.
Solution Approach 2:
The power semiconductor chip's lower surface inherently serves as an electrode, eliminating the need for separate bonding pads or connection structures on the chip背面. The chip structure itself provides the electrical connection interface, reducing manufacturing steps and costs while achieving compact stacking.
3Productivity
If the package volume is increased to accommodate multiple chips, then chips can be mounted, but electrical and mechanical reliability deteriorates due to temperature cycles
Solution Approach 1:
By stacking chips vertically rather than arranging them horizontally, the patent reduces the overall package volume while improving thermal management. The shorter distance between chips and the direct thermal path through the die attach paddle enhance heat dissipation efficiency, maintaining reliability under temperature cycles while achieving higher chip integration capacity.
Solution Approach 2:
The die attach paddle uses composite material structure (metal layer with adhesive) that provides both mechanical bonding strength and thermal conduction. This composite structure maintains electrical and mechanical reliability under temperature cycling while enabling compact chip stacking for higher integration capacity.
4Reliability
If conventional mounting methods are used, then chips can be electrically connected, but manufacturing cost increases due to complex wiring processes
Solution Approach 1:
The power semiconductor chip's lower surface inherently serves as an electrode, eliminating the need for separate bonding pads or connection structures on the chip背面. The chip structure itself provides the electrical connection interface, reducing manufacturing steps and costs while maintaining reliable electrical connection.
Solution Approach 2:
The patent extracts the wiring complexity from the chip interconnection process by using the lower surface of each chip as a direct electrode. This eliminates the need for complex wire bonding or through-silicon via routing between stacked chips. The electrical connection is achieved through the die attach paddle that directly contacts the lower surface electrode, simplifying the manufacturing process.
Data Source
AI summary
Provided is a power device package including: a substrate including at least one first die attach region; at least one first power semiconductor chip and at least one second power semiconductor chip that are stacked in order on the first die attach region; at least one die attach paddle that is disposed between the at least one first power semiconductor chip and the at least one second power semiconductor chip, wherein the die attach paddle comprises an adhesive layer that is attached to a top surface of the first power semiconductor chip; a conductive pattern including a second die attach region, on which the second semiconductor chip is mounted, and a wire bonding region that is electrically connected to the second die attach region; and an interlayer member between the adhesive layer and the conductive pattern; and a plurality of firs leads electrically connected to at least one of the at least one first power semiconductor chip and the at least one second power semiconductor chip.