Stacked Power Switch Gate Control for SOA Violation Protection
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Solution Overview
Problem
Integrated circuits using low voltage devices are prone to Safe Operating Area (SOA) violations when operated in high voltage environments, such as automotive applications, due to undervoltage or overvoltage conditions caused by PCB faults, which existing electrostatic discharge diodes cannot adequately prevent.
Innovation Solution
A power switch design incorporating stacked low voltage devices with analog multiplexers that dynamically adjust gate voltages based on undervoltage or overvoltage conditions, using reference voltages and detection circuits to prevent excessive voltages across device terminals.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If low voltage devices are used in IO circuits powered by higher battery voltage, then device integration and power efficiency are improved, but the devices become vulnerable to SOA violations during overvoltage or undervoltage conditions
Solution Approach 1:
The patent applies preliminary action by detecting overvoltage or undervoltage conditions before they can cause SOA violations. The detection circuit continuously monitors voltage conditions and triggers protective gate voltage adjustments in advance, preventing damage before it occurs rather than responding after damage happens.
Solution Approach 2:
The patent uses an intermediary approach by introducing a protection mechanism that mediates between the high voltage power domain and the low voltage devices. The protective circuit acts as an intermediary layer that translates high voltage conditions into appropriate gate voltage control signals, allowing LV devices to operate safely in HV environments without direct exposure to dangerous voltage levels.
2Object-affected harmful factors
If electrostatic discharge (ESD) diodes are used to clamp pad voltages, then voltage clamping is achieved, but this is insufficient for preventing SOA violations of LV devices
Solution Approach 1:
The patent extracts the protection function from the peripheral ESD diode structure and integrates it directly into the gate control mechanism of the power switch. Instead of relying on external clamping devices, the protection logic is taken out of the voltage clamping domain and embedded in the gate voltage generation circuitry, allowing direct control of device operation during fault conditions.
Solution Approach 2:
The patent implements feedback by continuously monitoring the voltage conditions at the pad and dynamically adjusting the gate voltage accordingly. When overvoltage or undervoltage conditions are detected, the feedback mechanism automatically modifies the gate voltage to keep the device within its safe operating area, creating a closed-loop protection system that responds in real-time to voltage variations.
Data Source
AI summary
A power switch includes a first transistor and a second transistor, coupled in series between a first power supply voltage and a pad. The power switch also includes an analog multiplexer (MUX). The MUX is configured to provide a pad voltage to a control electrode of the first transistor when an overvoltage (OV) condition is detected on the pad, a second power supply voltage to the control electrode of the first transistor when an undervoltage (UV) condition is detected on the pad, and a reference voltage to the control electrode of the first transistor when neither the UV condition nor the OV condition is detected on the pad. The first power supply voltage is greater than the second power supply voltage, and the reference voltage is a fraction of the first power supply voltage.