Stacked Semiconductor Power Distribution With TSV Signal Bypass
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Solution Overview
Problem
Placing a high-power logic component at the bottom of a heterogeneous stack in semiconductor systems leads to thermal challenges due to heat trapping by memory components, which complicates power distribution and serialized communications.
Innovation Solution
Implementing a distribution component, such as a distribution die or interposer, that includes power delivery circuitry and data serialization/deserialization circuitry to provide separate power and communicate signals directly with logic and memory components, bypassing interface circuitry through conductive vias.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If a high-power logic component is placed at the bottom of a heterogeneous stack, then power delivery and signal distribution are simplified, but thermal management deteriorates due to heat trapping by memory components
Solution Approach 1:
The patent inverts the conventional stack configuration by placing the high-power logic component at the top of the stack rather than at the bottom. This inversion allows heat to be rejected more efficiently through the memory components above it, resolving the thermal management issue while maintaining simplified power distribution through the use of through-silicon vias and redistribution layers.
2Quantity of substance
If memory components are stacked above a logic component, then integration density is improved, but heat rejection becomes difficult due to heat trapping
Solution Approach 1:
The patent inverts the stack configuration to place the logic component at the top, which enables the memory components below to act as heat sinks and facilitate heat rejection from the high-power logic device while maintaining high integration density through the stacked architecture.
3Reliability
If interface circuitry is used for power and signal distribution, then component coupling is achieved, but processing speed is reduced due to serialization overhead
Solution Approach 1:
The patent extracts the high-speed serial interface circuitry from the path between the logic component and memory components, using through-silicon vias to provide direct coupling. This eliminates the serialization/deserialization overhead while maintaining reliable component coupling through the extracted direct connection path.
Solution Approach 2:
The patent introduces through-silicon vias and redistribution layers as intermediaries to provide direct electrical coupling between the logic component and memory components, bypassing the need for serialization through interface circuitry and thereby improving processing speed while maintaining reliable coupling.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances thermal management by providing a direct heat rejection path, improves power density and processing speed, and supports higher processing density and user experience in electronic devices.
Implementation Method 1
bypassing interface circuitry through conductive vias
Implementation Method 2
power delivery circuitry configured to provide separate power to the logic component and the memory component
Data Source
AI summary
Methods, systems, and devices for power and signal distribution in stacked semiconductor systems are described. A semiconductor system may include a distribution component configured to communicate power, signals, or both with a logic component and memory component(s) of the semiconductor system. The distribution component may include power delivery circuitry to provide separate power to the memory component(s) and the logic component, data serialization/deserialization circuitry to communicate data signals with the logic component, or both. The distribution component may convey power, data signals, or both to the logic component using conductive vias that pass through the memory components and bypass interface circuitry of the memory component(s). The distribution component may include clock circuitry that receives, generates, or both, one or more clock signals and provides the one or more clock signals for I/O functionality of the distribution component, the logic component, the interface circuitry, or any combination thereof.