Stacked Quad Pre-Molded Packages for Substrate Area Reduction
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Solution Overview
Problem
There is a growing demand for increasing functionality and reducing the size of personal portable electronic products, which poses challenges in substrate area and cost management as the number of components increases, necessitating innovative packaging solutions to minimize board space while maintaining performance.
Innovation Solution
The development of a component package featuring a leadframe with a thin profile, where semiconductor dice and other components are stacked and packaged with electrically insulating material, allowing for a significant reduction in substrate area and enabling increased functionality without increasing costs, with leads providing signal transmission and interconnectivity between components.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If conventional quad packages are used for semiconductor dice, then electrical connectivity and functionality are achieved, but substrate area consumption increases and package thickness becomes excessive
Solution Approach 1:
The patent transitions from conventional planar package layouts to a vertical stacking architecture where multiple semiconductor dice are arranged in layers along the thickness dimension. This dimensional change allows multiple components to occupy the same substrate footprint while maintaining electrical connectivity through vertical interconnect structures, thereby reducing substrate area consumption without compromising functionality.
Solution Approach 2:
The patent implements a nested package structure where semiconductor dice are positioned within recesses of a leadframe, and insulating material is embedded within the leadframe structure itself. This nesting approach allows multiple components to be integrated within a compact volume, reducing the overall package footprint while maintaining structural integrity and electrical connectivity.
2Adaptability or versatility
If the number of assembled components increases to enhance functionality, then device performance improves, but substrate area and costs increase
Solution Approach 1:
By stacking semiconductor dice vertically in multiple layers, the patent enables increased device functionality through additional components without expanding the substrate footprint. The vertical arrangement allows more dice to be integrated within the same planar area, thereby enhancing adaptability and versatility while constraining substrate area growth.
Solution Approach 2:
The patent combines multiple semiconductor dice and insulating material structures into a single integrated package assembly. By merging these components into one unified package that can be mounted as a single unit on the substrate, the patent achieves enhanced functionality without proportionally increasing substrate area or assembly complexity.
3Area of stationary object
If package thickness is reduced to minimize board space, then substrate area utilization improves, but manufacturing complexity increases
Solution Approach 1:
The patent employs nested structures where insulating material is embedded within recesses of the leadframe, and semiconductor dice are positioned within leadframe cavities. This nesting approach enables thin package profiles while maintaining structural integrity through hierarchical integration of components, thereby reducing board space without proportionally increasing manufacturing complexity.
Solution Approach 2:
The patent utilizes composite structures combining conductive leadframe materials with embedded insulating materials in a single integrated package body. This composite approach allows the package to achieve reduced thickness while maintaining structural strength and electrical isolation, simplifying the overall package design compared to assembling separate thin components.
Data Source
AI summary
Pre-molded component packages that may be as thin as a leadframe for a semiconductor die, systems using the same, and methods of making the same are disclosed. The leads of an exemplary package are exposed at both surfaces at the leadframe. The packages may be stacked upon one another and electrically coupled at the exposed portions of their leads.