Stacked Product-Sum Semiconductor Circuit for Low-Power Neural Computing
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Solution Overview
Problem
Integrated circuits imitating the human brain face challenges with temperature-induced transistor characteristic changes, leading to increased power consumption and circuit size due to heat generation, especially in product-sum operations and hierarchical artificial neural networks.
Innovation Solution
A semiconductor device with layers of transistors using oxide semiconductors, particularly indium, zinc, and other elements, operates in subthreshold regions to perform product-sum operations with low power consumption and reduced circuit size, incorporating optical sensors for data conversion.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If a product-sum operation circuit is formed as an integrated circuit, then the operation speed is improved, but the temperature rises and transistor characteristics change
Solution Approach 1:
The patent divides the product-sum operation circuit into multiple independent operation units that can perform calculations in parallel. By segmenting the computational workload across multiple units, the system achieves high-speed processing without concentrating excessive heat generation in a single location, thus maintaining transistor characteristic stability.
Solution Approach 2:
The patent transitions from planar circuit arrangement to a three-dimensional stacked structure with multiple layers. This vertical dimensionality change increases processing speed by enabling parallel operations across layers while distributing heat generation in the vertical direction, preventing localized overheating that would alter transistor characteristics.
2Measurement precision
If digital multiplier and addition circuits are designed for multi-bit arithmetic operation, then the calculation precision is improved, but the circuit area expands
Solution Approach 1:
The patent segments the multi-bit arithmetic operation into multiple single-bit operation units arranged in parallel. Each unit handles a specific bit position, and the overall precision is achieved through the combined output of these segmented units. This segmentation allows high-precision calculation without requiring a single large complex circuit, thus reducing total circuit area.
Solution Approach 2:
The patent uses multiple simple single-bit operation units instead of one complex multi-bit unit. By employing multiple partial operations (single-bit calculations) that collectively achieve the full multi-bit precision, the system attains high calculation accuracy while keeping each individual unit small, thereby reducing overall circuit area.
3Productivity
If the number of arithmetic circuits is increased for hierarchical artificial neural network, then the processing capability is improved, but the power consumption increases
Solution Approach 1:
The patent merges multiple arithmetic circuits into a unified structure where operation units are shared across different layers of the hierarchical neural network. By combining resources and enabling reuse of the same hardware units for multiple computational layers, the system achieves high processing capability without proportionally increasing power consumption.
Solution Approach 2:
The patent designs arithmetic circuits with universal functionality that can perform the same operations across multiple layers of the neural network. Each operation unit is multi-functional, serving different computational purposes in different layers, thereby increasing processing capability without requiring separate dedicated circuits for each layer, which would exponentially increase power consumption.
Data Source
AI summary
A semiconductor device with low power consumption is provided. The semiconductor device includes a first layer and a second layer. The first layer includes a first cell and a first to a third circuit, and the second layer includes a second cell and a fourth and a fifth circuit. The first, second, and fourth circuits each have a function of converting digital data into analog current. The first cell calculates a product of a value from the first current and a value from the second circuit and inputs a calculation result into a third circuit as current. The third circuit generates analog current from the input current. The second cell calculates a product of a value from the third circuit and a value from the fourth circuit and inputs a calculation result into the fifth circuit as current. The fifth circuit generates analog current from the input current.