Stacked PSRAM-on-SoC Semiconductor Structure for Lower Power
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Solution Overview
Problem
The integration of embedded memory in System on Chip (SoC) increases manufacturing cost, complexity, and limits the area and performance of integrated circuits, while also leading to higher power consumption.
Innovation Solution
A semiconductor structure comprising a semiconductor die with a component layer and a pseudo static random access memory (PSRAM) die, where the PSRAM die is attached to the semiconductor die, utilizing an organic layer and a passivation layer for electrical connection and protection, and a keep out zone to isolate the PSRAM die from the component layer.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If embedded memory (SRAM/DRAM) is integrated in the SoC, then computing efficiency is improved, but manufacturing cost and process complexity increase
Solution Approach 1:
The patent divides the memory system into two separate parts: the SoC chip and a standalone memory chip. The SoC chip focuses on processing functions while the memory chip provides storage, eliminating the need to integrate complex memory structures within the SoC. This segmentation resolves the contradiction by maintaining computing efficiency through close coupling while simplifying manufacturing processes for each individual chip.
Solution Approach 2:
The patent transitions from planar integration (embedding memory within the SoC substrate) to three-dimensional stacking (placing memory chip on top of SoC chip via SiP technology). This dimensional change allows memory and processing to coexist in close proximity without increasing the footprint or complicating the manufacturing of either component.
2Productivity
If embedded memory (SRAM/DRAM) is integrated in the SoC, then computing efficiency is improved, but the area and performance of other integrated circuits are limited
Solution Approach 1:
By separating memory and processing onto different chips, the patent eliminates the area that would be consumed by embedded memory structures within the SoC. This allows the SoC to be optimized for processing performance without area constraints from memory integration, while the memory chip provides adequate storage capacity in a dedicated space.
Solution Approach 2:
The SiP technology enables vertical stacking of memory and processing chips, transitioning from lateral area consumption to vertical space utilization. This dimensional change preserves the area for high-performance integrated circuits while providing sufficient memory capacity through the stacked architecture.
3Quantity of substance
If embedded memory (SRAM/DRAM) is integrated in the SoC, then memory capacity is provided, but power consumption increases
Solution Approach 1:
The patent separates memory and processing functions onto different chips, allowing each to be optimized independently for power efficiency. The memory chip can use lower-power memory technologies while the processing chip manages memory access efficiently, reducing overall system power consumption compared to integrated embedded memory solutions.
Data Source
AI summary
A semiconductor structure including a semiconductor die, a component layer and a pseudo static random access memory (PSRAM) die is provided. The component layer is disposed on the surface of the semiconductor die, wherein the component layer includes an organic layer. The PSRAM die is disposed on the surface of the semiconductor die and is electrically connected to the semiconductor die. A manufacturing method of a semiconductor structure is also provided.