3D Stacked PUF Transistor Cell for Higher Randomness

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Solution Overview

Problem

Existing physical unclonable functions (PUFs) in semiconductor devices face limitations in randomness and area efficiency, particularly in applications requiring high security, such as cryptography, due to the lack of sufficient variation in source/drain interface parasitic resistances.

Innovation Solution

The proposed semiconductor device design stacks transistors in a columnar configuration, forming source/drain structures that directly contact to create boundaries with randomly distributed resistances, increasing the randomness and reducing the area required for each transistor cell by eliminating unnecessary stacking.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Manufacturing precision

If transistors are arranged in conventional planar configuration, then manufacturing is simpler, but area efficiency is poor and randomness is insufficient

Engineering Contradiction:
Improvesource/drain interface parasitic resistance variationVSAvoidtransistor cell area
Core Design Contradiction:
Manufacturing precisionVSArea of stationary object

Solution Approach 1:

The patent transitions from conventional planar transistor arrangement to a three-dimensional stacked configuration where multiple transistors are vertically arranged. This dimensional change allows source/drain structures from different transistors to directly contact and form interfaces, increasing the number of parasitic resistance interfaces within a compact area while maintaining manufacturing feasibility through standard CMOS processes.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

Solution Approach 2:

The patent merges source/drain structures of multiple transistors by having them directly contact to form shared interfaces. This merging creates additional parasitic resistance interfaces that would not exist in isolated transistor configurations, thereby enhancing randomness without proportionally increasing the transistor cell area.

Inventive Principle:
Principle #5Merging (Combining)

2Reliability

If more transistors are added to increase randomness, then output bit randomness improves, but transistor cell area increases

Engineering Contradiction:
Improveoutput bit randomnessVSAvoidtransistor cell area
Core Design Contradiction:
ReliabilityVSArea of stationary object

Solution Approach 1:

By stacking transistors vertically in three dimensions, the patent achieves higher transistor density within the same footprint. Multiple transistors share common source/drain regions, creating additional interfaces and parasitic resistances that enhance randomness without linearly increasing the area occupied by each transistor cell.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

Solution Approach 2:

The stacked transistor structure serves multiple functions simultaneously: it provides the necessary randomness through multiple parasitic resistance interfaces while maintaining compact area efficiency. The shared source/drain structures between transistors create additional measurement points and variability sources within a single transistor cell.

Inventive Principle:
Principle #6Universality (Multi-functionality)

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This design enhances the randomness of output bits while minimizing the area needed for each transistor cell, improving the security and efficiency of PUFs in semiconductor devices.

Implementation Method 1

source/drain structures that directly contact to create boundaries with randomly distributed resistances

Methodology Applied
Scientific EffectParasitic resistance: Electrical Resistance

Data Source

PatentUS12598801B2Semiconductor device of physical unclonable function and manufacturing method thereof
Publication Date: 2026.04.07 TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD
  • US12598801B2 patent drawing
  • US12598801B2 patent drawing
  • US12598801B2 patent drawing

AI summary

A semiconductor device includes a first transistor cell. The first transistor cell generates a first current signal and a second current signal indicating a bit of a physical unclonable function. The first transistor cell includes a first transistor, a second transistor and a third transistor. The first transistor outputs the first current signal. The second transistor generates the first current signal from a first source/drain structure of the second transistor, and generates the second current signal from a second source/drain structure of the second transistor. The third transistor outputs the second current signal. The first transistor, the second transistor and the third transistor are stacked in order along a first direction. The first source/drain structure of the second transistor and the second source/drain structure of the second transistor are arranged along a second direction different from the first direction.