Stacked Pull-Up Memory Elements for Soft Error Immunity
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Solution Overview
Problem
Volatile memory elements in integrated circuits face challenges with decreased read and write margins due to lower power supply voltages and smaller device sizes, leading to unreliable operation and susceptibility to soft error upsets from radiation strikes.
Innovation Solution
The implementation of memory cells with stacked pull-up transistors and reverse-biased pull-down transistors in cross-coupled inverting circuits, which provide improved noise margins and immunity to soft error upsets by allowing the memory element to recover from temporary voltage perturbations caused by radiation strikes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If lower power supply voltages and smaller device sizes are used to scale semiconductor technology, then device density and integration are improved, but read and write margins for volatile memory elements decrease
Solution Approach 1:
The pull-up function is segmented into multiple stacked transistors (first pull-up transistor and second pull-up transistor) instead of using a single transistor. This segmentation allows the memory element to maintain adequate drive strength and noise margins even when individual transistor sizes are reduced for higher density scaling.
Solution Approach 2:
The invention changes the electrical parameters of the memory element by introducing stacked transistors with specific threshold voltage characteristics. The first pull-up transistor has a first threshold voltage and the second pull-up transistor has a second threshold voltage, creating optimized voltage transfer characteristics that maintain read/write margins at lower supply voltages.
2Device complexity
If conventional cross-coupled inverter structures are used in volatile memory elements, then circuit simplicity is maintained, but immunity to soft error upsets from radiation strikes is insufficient
Solution Approach 1:
The stacked pull-up transistor structure provides beforehand cushioning against radiation-induced soft errors. The multiple transistors create inherent noise filtering and voltage stabilization that prevents temporary voltage perturbations from causing state flips, cushioning the memory element against radiation strikes before they can cause errors.
Solution Approach 2:
The invention converts the potential harm of radiation strikes into a beneficial filtering effect. The stacked transistor structure with different threshold voltages creates a noise filter that transforms high-energy radiation-induced voltage spikes into harmless signals that cannot flip the memory state, turning a harmful effect into a benefit.
Data Source
AI summary
Integrated circuits with memory cells are provided. A memory cell may include first and second cross-coupled inverting circuits configured to store a single data bit. The first inverting circuit may have an output serving as a first data storage node for the memory cell, whereas the second inverting circuit may have an output serving as a second data storage node for the memory cell. Access transistors may be coupled between the first and second data storage nodes and corresponding data lines. Each of the first and second inverting circuit may have a pull-down transistor and at least two pull-up transistors stacked in series. The pull-down transistors may have body terminals that are reverse biased to help reduce leakage current through the first and second inverting circuits. The memory cell may be formed using a narrower two-gate configuration or a wider four-gate configuration.