Stacked Quantum Chip Layout for Low-Loss Qubit Circuits
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Solution Overview
Problem
In quantum computing, deposited dielectric materials cause high energy loss and decoherence in quantum circuit elements, limiting the performance of quantum processors due to their proximity to qubits, even when arranged on separate chips.
Innovation Solution
The solution involves arranging circuit elements with lossy dielectrics on the backside of a carrier chip, away from qubits, while keeping high-coherence circuit elements on the front side, and using bump bonds and connectors made of superconductor materials to minimize energy loss and decoherence.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If dielectric materials are deposited near qubits to support circuit elements, then structural support and electrical isolation are provided, but energy loss and decoherence increase
Solution Approach 1:
The patent applies dimensional separation by stacking quantum device layers vertically. Qubits are placed on one substrate layer while dielectric-supported circuit elements are placed on a separate layer above or below, connected via through-substrate connectors. This vertical arrangement removes dielectric materials from direct proximity to qubits, reducing energy loss while maintaining circuit functionality through the third dimension.
Solution Approach 2:
The patent introduces through-substrate connectors as intermediary elements that bridge the gap between qubit circuits and dielectric-supported circuit elements. These connectors transmit signals and power through the substrate without requiring dielectric materials adjacent to qubits, acting as a mediator that enables functional connection while eliminating the harmful dielectric-qubit proximity.
2Area of stationary object
If circuit elements are placed close to qubits for compact design, then device area is reduced, but energy loss and decoherence increase
Solution Approach 1:
The patent utilizes vertical stacking to achieve compact integration without horizontal proximity. Circuit elements are positioned in the vertical dimension (above or below qubit layer) rather than adjacent in the horizontal plane, maintaining small device footprint while eliminating energy loss associated with close qubit-circuit element spacing.
Solution Approach 2:
The patent segments the quantum device into functionally separate layers: a qubit layer and a circuit element layer. This segmentation allows each layer to be optimized independently - qubits can maintain their low-loss environment while circuit elements have full access to dielectric support materials, achieving compact integration without compromise.
3Stability of the object's composition
If dielectric materials are used for electrical isolation and support, then structural stability is improved, but coherence of quantum circuit elements deteriorates
Solution Approach 1:
The patent relocates dielectric materials from the horizontal plane near qubits to vertical layers separated by through-substrate connectors. This dimensional relocation maintains the structural stability and electrical isolation functions of dielectrics while removing their harmful influence on qubit coherence through spatial separation in the vertical dimension.
Solution Approach 2:
The through-substrate connector acts as an intermediary that transmits electrical signals and power through the substrate without requiring dielectric materials in direct contact with qubits. This mediator enables the use of dielectric-supported circuit elements while protecting qubit coherence by eliminating direct dielectric-qubit interfaces.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration reduces energy loss and dissipation in quantum circuit elements, maintaining high coherence and low decoherence, thereby enhancing the performance of quantum processors.
Implementation Method 1
The second chip includes a single layer of superconductor material on the first surface of the substrate, the single layer of superconductor material including a first circuit element
Data Source
AI summary
A device includes: a first chip including a qubit; and a second chip bonded to the first chip, the second chip including a substrate including first and second opposing surfaces, the first surface facing the first chip, wherein the second chip includes a single layer of superconductor material on the first surface of the substrate, the single layer of superconductor material including a first circuit element. The second chip further includes a second layer on the second surface of the substrate, the second layer including a second circuit element. The second chip further includes a through connector that extends from the first surface of the substrate to the second surface of the substrate and electrically connects a portion of the single layer of superconducting material to the second circuit element.