3D Stacked Quantum Chip Architecture for Qubit Connectivity
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Solution Overview
Problem
Current quantum chip designs face challenges in optimizing qubit arrangement and connectivity, leading to limited computing power and accuracy, which hinders the development of more efficient quantum processors and computers.
Innovation Solution
The proposed solution involves a quantum chip architecture with a qubit array arranged in a surface code structure of M rows by N columns, where qubits are placed on the top sheet and reading cavities and other devices are on the bottom sheet, enhancing connectivity and coherence, and allowing for a separate layout that moves destructive processes out of the bit sample layer.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If qubits are arranged in a traditional layout on a single layer, then the chip structure is simple, but the connectivity between qubits is poor and the quantum volume is limited
Solution Approach 1:
The patent transitions from a traditional single-layer qubit arrangement to a three-dimensional stacked architecture with top and bottom sheets. Qubits are positioned on the top sheet while reading cavities are positioned on the bottom sheet, utilizing vertical stacking to enhance connectivity without increasing lateral complexity. This dimensional change allows multiple qubits to share common reading cavities, improving quantum volume while maintaining manageable structural complexity.
2Ease of manufacture
If destructive devices and processing techniques are placed in the bit sample layer, then the manufacturing process is simplified, but the coherence of qubits deteriorates and wiring space is reduced
Solution Approach 1:
The patent divides the quantum chip into distinct functional layers: the top sheet contains qubits and wiring, while the bottom sheet contains reading cavities and destructive devices. This segmentation separates qubit-sensitive regions from manufacturing-intensive regions, allowing destructive processing techniques to be applied to the bottom sheet without compromising qubit coherence. The layered structure enables independent optimization of manufacturing ease and qubit reliability.
3Quantity of substance
If more qubits are added to increase computing power, then the number of bits increases, but the accuracy of chip processing decreases
Solution Approach 1:
The patent implements a shared reading cavity architecture where multiple qubits on the top sheet can be read through common reading cavities on the bottom sheet. This universal reading mechanism reduces the total number of independent reading paths needed, thereby maintaining processing accuracy while scaling the number of qubits. The shared cavity system provides a stable, standardized interface that preserves measurement precision across multiple qubits.
Data Source
AI summary
This application discloses methods and devices for a quantum chip, a quantum processor and a quantum computer, and relates to the field of quantum technology. The quantum chip includes a bottom sheet and a top sheet; a qubit array disposed on the top sheet, the qubit array comprising a plurality of qubits distributed in an array structure of M rows by N columns, and M and N being both integers greater than 1; a reading cavity disposed on the bottom sheet, and the reading cavity being configured to acquire status information of a qubit in the qubit array; and the bottom sheet and the top sheet being electrically connected.