Stacked Qubit Substrates Relay Wiring Multiplexing

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Solution Overview

Problem

Existing qubit devices face challenges in efficiently integrating and controlling multiple qubits due to increased complexity and crosstalk issues as the number of qubits grows, which complicates the fabrication process and reduces computational performance.

Innovation Solution

The proposed qubit device configuration includes a first qubit substrate, a second qubit substrate, and a first relay substrate interposed between them. This configuration allows for the connection of qubits through capacitors on the relay substrate, enabling multiplexing of response signals and reducing the number of wiring lines needed.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If the number of qubits is increased to enhance computational performance, then the computational capability is improved, but the number of wiring lines and control signals increases, leading to increased device complexity and crosstalk

Engineering Contradiction:
Improvecomputational performanceVSAvoidwiring line complexity
Core Design Contradiction:
ProductivityVSDevice complexity

Solution Approach 1:

The patent merges multiple read-out lines into a single shared read-out line that can read out quantum states from multiple qubits sequentially. This is achieved by time-multiplexing the read-out process, where the same read-out electrode and transmission line are used to access different qubits at different times, thereby reducing the total number of wiring lines needed while maintaining the ability to read out multiple qubits

Inventive Principle:
Principle #5Merging (Combining)

Solution Approach 2:

The read-out electrode and transmission line are designed with multi-functionality, serving as universal interfaces that can read out quantum states from multiple different qubits. The control signal transmission lines are also designed to be shared across multiple qubit pairs, allowing a single line to perform multiple read-out operations sequentially, thereby reducing overall device complexity

Inventive Principle:
Principle #6Universality (Multi-functionality)

2Productivity

If the number of qubits is increased to enhance computational performance, then the computational capability is improved, but crosstalk between control signals and read-out signals increases, reducing measurement precision

Engineering Contradiction:
Improvecomputational performanceVSAvoidqubit state read-out precision
Core Design Contradiction:
ProductivityVSMeasurement precision

Solution Approach 1:

The patent segments the control signal transmission and read-out signal transmission into separate physical paths. Control signals are transmitted through dedicated control signal transmission lines that are spatially separated from the read-out lines. This segmentation prevents crosstalk between control and read-out signals, maintaining measurement precision even as the number of qubits increases

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent introduces intermediate coupling elements (such as capacitive couplers or inductive couplers) between qubits and read-out electrodes. These intermediaries enable quantum state read-out without requiring direct strong coupling, thereby reducing crosstalk and interference between adjacent qubits and control lines while maintaining sufficient read-out fidelity

Inventive Principle:
Principle #24Intermediary (Mediator)

3Productivity

If more qubits are added to increase computational capability, then the number of qubit combinations increases, but the layout design becomes more complex and fabrication difficulty increases

Engineering Contradiction:
Improvecomputational capabilityVSAvoidfabrication process simplicity
Core Design Contradiction:
ProductivityVSEase of manufacture

Solution Approach 1:

The patent transitions from a two-dimensional planar layout to a three-dimensional stacked architecture, with qubits arranged on multiple substrates layered vertically. This dimensional change allows for increased qubit capacity without proportionally increasing the planar area, simplifying layout design and fabrication by utilizing vertical stacking rather than expanding horizontal footprint

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

Solution Approach 2:

The patent employs a nested substrate structure where multiple qubit substrates are stacked and interconnected through relay substrates. The relay substrates are nested between qubit substrates, creating a hierarchical layered structure. This nesting approach modularizes the fabrication process, allowing each layer to be fabricated and tested independently before assembly, thereby reducing overall fabrication complexity

Inventive Principle:
Principle #7Nested doll (Nesting)

Data Source

PatentUS20250200415A1Qubit device and qubit device fabrication method
Publication Date: 2025.06.19 FUJITSU LTD
  • US20250200415A1 patent drawing
  • US20250200415A1 patent drawing
  • US20250200415A1 patent drawing

AI summary

A quantum bit device that includes: a first qubit substrate; a second qubit substrate; and a first relay substrate provided between the first qubit substrate and the second qubit substrate, wherein: the first qubit substrate includes a first qubit, a first control electrode, and a first read-out electrode; the second qubit substrate includes a second qubit, a second control electrode, and a second read-out electrode; and the first relay substrate includes a first control line that is connected to the first control electrode, and transmits a control signal that controls the first qubit, a read-out line that is a line connected to both the first read-out electrode and the second read-out electrode, and that transmits a response signal indicating a state of the first qubit or the second qubit, a first access electrode connected to the control line, and a second access electrode connected to the read-out line.