Stacked Qubit Chip Layout With Shielded 3D Control Integration
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Solution Overview
Problem
In quantum computing, superconducting qubits face decoherence and layout constraints due to interactions with lossy materials and control wiring, limiting qubit density and coupling capabilities in existing designs.
Innovation Solution
The solution involves separating qubit-containing chips with high-quality materials from chips with lossy materials and control wiring, using 3D integration with superconductor bump bonds, and shielding to reduce decoherence, while relaxing layout constraints by moving control and readout elements to a separate chip.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If qubits are integrated with control wiring and lossy materials on the same chip, then device complexity is reduced and ease of manufacture is improved, but qubit coherence is degraded due to interactions with lossy materials
Solution Approach 1:
The device is divided into two separate chips: a first chip containing superconducting qubits with high-quality materials, and a second chip containing control wiring and lossy materials. This segmentation isolates qubits from lossy materials while maintaining functional integration through 3D stacking and bump bonds, resolving the contradiction between ease of manufacture and qubit coherence.
Solution Approach 2:
A shielding layer is introduced as an intermediary between the qubits on the first chip and the control wiring on the second chip. This shielding layer reduces electromagnetic interference and harmful interactions while allowing the device to maintain its integrated functionality, thus preserving qubit coherence without sacrificing ease of manufacture.
2Productivity
If qubit density is increased through closer integration, then productivity is improved, but harmful interactions with control elements and wiring increase
Solution Approach 1:
The invention transitions from 2D planar integration to 3D vertical integration by stacking the qubit chip and control chip vertically. This dimensional change allows qubits to be densely packed on the first chip while control wiring resides on the second chip, enabling high qubit density without increasing harmful lateral interactions between qubits and control elements.
Solution Approach 2:
By separating qubits and control wiring into different chips within a stacked architecture, the invention enables independent optimization of qubit density on the first chip while maintaining controlled interactions through the shielding layer and selective bump bond connections, thus achieving high productivity without excessive harmful interactions.
3Device complexity
If control wiring is placed on the same chip as qubits, then device complexity is reduced, but layout constraints increase due to wiring routing requirements
Solution Approach 1:
The invention resolves layout constraints by moving control wiring from the same plane as qubits to a vertical dimension on a separate chip. This 3D arrangement eliminates planar routing conflicts and allows independent optimization of qubit layouts and wiring layouts without mutual interference, while the stacked architecture maintains overall device simplicity.
4Reliability
If shielding layers are added to protect qubits from control wiring, then qubit coherence is improved, but device complexity and manufacturing steps increase
Solution Approach 1:
The shielding layer is integrated into the second chip's structure during its fabrication process rather than being added as a separate step between chips. This segmentation of functions into dedicated layers during manufacturing reduces overall device complexity while maintaining the protective function against electromagnetic interference.
Solution Approach 2:
The shielding layer is combined with the control chip structure itself, serving dual purposes: as part of the control wiring substrate and as a protective shield for qubits. This merging reduces the number of separate components and manufacturing steps, thus reducing device complexity while maintaining qubit coherence protection.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances qubit density, coherence, and coupling by isolating qubits from lossy materials, reducing energy loss and decoherence, and maintaining high quality factors, thereby improving the performance of quantum computing processors.
Implementation Method 1
superconducting qubits for use in performing data processing operations
Implementation Method 2
the control wiring may be covered by a shielding layer and a dielectric layer
Data Source
Figure 1A~1B
Figure 2A
Figure 2B
AI summary
A stacked quantum computing device including a first chip that includes a first dielectric substrate and a superconducting qubit on the first dielectric substrate, and a second chip that is bonded to the first chip and includes a second dielectric substrate, a qubit readout element on the second dielectric substrate, a control wire on the second dielectric substrate, a dielectric layer covering the control wire, and a shielding layer covering the dielectric layer.