Stacked RC Delay Cell for RF Transceiver Area Reduction

The patent merges multiple capacitors (first capacitor at first level, second capacitor at second level, and third capacitor at third level) with a single resistor to form one RC delay cell, replacing the conventional one-to-one configuration. This combining approach increases the total capacitance value without proportionally increasing the chip area, thereby improving RC delay performance while reducing footprint.

The patent transitions from a planar one-to-one RC configuration to a three-dimensional stacked architecture where capacitors are arranged at different vertical levels (first, second, and third levels) above the same substrate region. This vertical stacking enables multiple capacitors to share the same footprint area, significantly reducing the horizontal chip area required while accumulating sufficient total capacitance for adequate RC delay.

The patent combines three separate capacitors (at different levels) into a single functional unit that works with one resistor to produce the desired RC delay effect. The total capacitance is the sum of individual capacitors (C_total = C1 + C2 + C3), achieving sufficient delay without requiring three separate RC cells and their associated resistors, thereby reducing overall footprint.

By stacking capacitors vertically at different levels rather than placing them horizontally adjacent to each other, the patent enables multiple capacitance elements to occupy overlapping footprint areas. This dimensional transition allows the circuit to achieve increased RC delay (through higher total capacitance) while constraining the horizontal chip footprint to a compact region.

The patent segments the capacitor formation process into distinct fabrication stages corresponding to different interconnect levels. The first capacitor is formed using first conductive plates and first dielectric layers, the second capacitor using second conductive plates and second dielectric layers, and the third capacitor using third conductive plates and third dielectric layers. This segmentation allows each capacitor to be fabricated using standard multi-layer capacitor techniques already present in deep sub-micron CMOS processes, making the stacked configuration compatible with existing manufacturing capabilities.

The stacked capacitor structure leverages the multi-layer interconnect architecture already present in deep sub-micron CMOS technology. Each level of the stack utilizes standard conductive plates, dielectric layers, and via connections that are routinely fabricated in modern semiconductor manufacturing. This approach repurposes existing fabrication infrastructure and design rules to create the three-dimensional capacitor array, avoiding the need for specialized or additional fabrication steps.