Stacked Redistribution Semiconductor Package for High-Density Integration
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing semiconductor packages face challenges in achieving high integration density, miniaturization, and reducing fabrication costs while maintaining reliability.
Innovation Solution
A semiconductor package design incorporating multiple redistribution substrates with insulating layers, conductive structures, and mold layers, along with semiconductor chips connected by bumps, to create a high-density package with reduced costs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If multiple redistribution substrates and semiconductor chips are stacked to increase integration density, then the number of components and structural complexity increase
Solution Approach 1:
The patent implements a stacked configuration where the first redistribution substrate, first semiconductor chip, second redistribution substrate, and second semiconductor chip are vertically nested. Each layer is positioned on top of the previous layer, with mold layers filling the spaces between them. This nesting approach maximizes integration density by utilizing vertical space while organizing multiple components in a compact hierarchical structure.
Solution Approach 2:
The patent transitions from a planar arrangement to a three-dimensional stacked configuration. By arranging redistribution substrates and semiconductor chips in vertical layers rather than side-by-side on a single plane, the design achieves higher integration density within a smaller footprint area, effectively utilizing the vertical dimension to increase component capacity.
2Reliability
If multiple mold layers are used to encapsulate stacked components, then manufacturing precision and alignment requirements increase
Solution Approach 1:
The patent divides the encapsulation into multiple separate mold layers: a first mold layer between the first redistribution substrate and second redistribution substrate, and a second mold layer on the second redistribution substrate and second semiconductor chip. This segmentation allows each mold layer to be applied and cured independently, reducing the cumulative alignment complexity that would result from attempting to apply a single thick mold layer over the entire stacked structure.
Solution Approach 2:
The first mold layer is applied and cured before the second redistribution substrate and second semiconductor chip are fully assembled. This preliminary encapsulation stabilizes the lower portion of the stack, providing a rigid foundation that simplifies subsequent alignment and assembly operations, thereby reducing the overall manufacturing precision requirements for the complete structure.
Data Source
AI summary
Provided is a semiconductor package, including a first redistribution substrate, a first semiconductor chip on the first redistribution substrate, first bumps between the first redistribution substrate and the first semiconductor chip, a conductive structure on the first redistribution substrate and spaced apart from the first semiconductor chip, a second redistribution substrate on the first semiconductor chip, second bumps between the first semiconductor chip and the second redistribution substrate, a second semiconductor chip on the second redistribution substrate, a first mold layer between the first redistribution substrate and the second redistribution substrate, and on the first semiconductor chip, and a second mold layer on the second redistribution substrate and the second semiconductor chip, and spaced apart from the first mold layer.