Stacked Redistribution Semiconductor Package for Terminal Interference
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing semiconductor packages face challenges in maintaining connection reliability and preventing interference between high-density connection terminals, particularly in compact and multifunctional electronic devices.
Innovation Solution
The semiconductor package employs a dual redistribution structure with multiple layers and conductive blocks to increase the gap between connection terminals, enhance heat dissipation, and improve signal integrity through a combination of redistribution patterns and conductive posts.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If connection terminals are arranged in high density, then the semiconductor package achieves higher integration, but interference between connection terminals increases
Solution Approach 1:
The patent introduces a third vertical dimension by stacking redistribution structures above and below the semiconductor chip. This allows connection terminals to be distributed across multiple layers (first redistribution structure below chip, second redistribution structure above chip), effectively reducing horizontal density and interference while maintaining high integration through vertical expansion.
2Reliability
If connection terminals are spaced further apart to prevent interference, then terminal reliability improves, but the semiconductor package area increases
Solution Approach 1:
The patent moves connection terminals from a two-dimensional horizontal layout to a three-dimensional stacked configuration. By placing some terminals on the first redistribution structure below the chip and others on the second redistribution structure above the chip, the effective terminal spacing increases without expanding the horizontal package footprint.
3Object-affected harmful factors
If multiple redistribution layers are added to increase terminal gap, then interference is reduced, but device complexity increases
Solution Approach 1:
The patent divides the redistribution function into separate segments: a first redistribution structure below the chip handling certain connections, and a second redistribution structure above the chip handling other connections. This segmentation reduces the complexity of any single redistribution layer while achieving the overall goal of reduced terminal interference.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration enhances the reliability and performance of semiconductor packages by reducing interference, improving heat dissipation, and maintaining efficient signal transmission, thereby supporting the demands of highly integrated semiconductor chips in compact electronic devices.
Implementation Method 1
A plurality of conductive blocks each has a wall shape extending in a horizontal direction between the first redistribution structure and the second redistribution structure. The plurality of conductive blocks directly contacts the first redistribution structure and the second redistribution structure... The plurality of conductive blocks comprises a heat dissipation block
Data Source
AI summary
A semiconductor package includes a first redistribution structure comprising a plurality of first redistribution layers. A second redistribution structure is above the first redistribution structure. The second redistribution structure comprises a plurality of second redistribution layers. A first semiconductor chip is on the first redistribution structure and is arranged between the first redistribution structure and the second redistribution structure. A conductive block directly contacts the first redistribution structure and the second redistribution structure and extends in a horizontal direction between the first redistribution structure and the second redistribution structure. A plurality of conductive posts is around the first semiconductor chip and the conductive block. The plurality of conductive posts extends in a vertical direction and directly contacts the first redistribution structure and the second redistribution structure.