Stacked Redistribution Substrates for Compact Semiconductor Packaging
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Solution Overview
Problem
Existing semiconductor packages face challenges with compact size, handling, and testing of small solder balls, as well as the need for diversified mount boards due to the decreasing size of semiconductor chips. Additionally, fan-out panel semiconductor packages often result in an excessively large area for redistribution lines compared to the semiconductor chip.
Innovation Solution
A semiconductor package is designed with a first redistribution substrate, a second redistribution substrate, and vertical connection structures to connect them electrically. The package includes a first semiconductor chip with pads on its surface, a second semiconductor chip, and a molding layer to enhance structural stability and electrical properties.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of operation
If fan-out panel semiconductor packages are used to address small chip size issues, then handling and testing of small chips is improved, but the area of redistribution lines becomes excessively large
Solution Approach 1:
The package structure is divided into multiple segments: a first redistribution substrate with first redistribution lines, a second redistribution substrate with second redistribution lines, and a first semiconductor chip mounted on the first redistribution substrate. This segmentation allows the redistribution functions to be distributed across multiple substrates, reducing the area required for redistribution lines on any single substrate while improving handling and testing capabilities.
2Productivity
If semiconductor chip size is reduced for high integration, then integration density is improved, but adherence and handling of solder balls becomes difficult
Solution Approach 1:
The first redistribution substrate acts as an intermediary between the small first semiconductor chip and the mounting structure. The substrate provides a larger area for solder ball placement and handling compared to the small chip itself, making adherence and handling easier while maintaining the high integration density achieved through small chip size.
3Area of stationary object
If multiple redistribution substrates are stacked to reduce area, then electrical connection complexity increases
Solution Approach 1:
The package structure employs a nested arrangement where the first semiconductor chip is mounted on the first redistribution substrate, which is stacked with the second redistribution substrate. The wiring pattern of the second redistribution substrate is coupled to the pads of the first semiconductor chip through vertical connection structures, creating a nested, multi-layer configuration that reduces footprint while organizing electrical connections in a structured manner.
Data Source
AI summary
A semiconductor package includes a first redistribution substrate, a first semiconductor chip having first pads on the first semiconductor chip, a second redistribution substrate on the first semiconductor chip, a first vertical connection structure through which the first and second redistribution substrates are electrically connected on one side of the first semiconductor chip, a second semiconductor chip on the second redistribution substrate, a first molding layer that covers the second semiconductor chip on the second redistribution substrate, a third redistribution substrate on the first molding layer; and a second vertical connection structure which is coupled to the second redistribution substrate and through which the second and third redistribution substrates are electrically connected on one side of the second semiconductor chip. A wiring pattern of the second redistribution substrate is coupled to the first pads of the first semiconductor chip.