3D Stacked Reference Voltage Generator for IC Packing Density

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Solution Overview

Problem

Conventional reference-voltage-generators occupy a large footprint in integrated circuits, limiting packing density and semiconductor real estate efficiency, and there is a need for more compact solutions that provide accurate and controllable reference voltages.

Innovation Solution

The integration of resistive components and switches within a multi-deck assembly structure, where resistive units are similar to memory cells but with interconnecting units instead of capacitors, forming a resistor-divider-circuit that conserves space and allows for precise control of the reference voltage output.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Measurement precision

If conventional reference-voltage-generators are used, then accurate and controllable reference voltage is achieved, but large footprint is occupied

Engineering Contradiction:
Improvereference voltage accuracyVSAvoidfootprint area
Core Design Contradiction:
Measurement precisionVSArea of stationary object

Solution Approach 1:

The patent transitions from planar 2D layout to 3D vertical stacking by implementing multiple decks (first deck, second deck, third deck) stacked vertically. The resistive components are distributed across different vertical levels, with interconnect structures connecting corresponding components on adjacent decks. This three-dimensional arrangement dramatically reduces the horizontal footprint while preserving the functional integrity and accuracy of the reference voltage generation circuit.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

Solution Approach 2:

The patent embeds multiple functional layers within a compact vertical structure. Each deck contains resistive components and interconnect structures that are nested within the overall assembly. The first deck, second deck, and third deck are stacked and interconnected, with each deck containing simplified versions of the functional elements found in conventional designs, thereby achieving space efficiency without sacrificing measurement precision.

Inventive Principle:
Principle #7Nested doll (Nesting)

2Quantity of substance

If packing density is increased, then semiconductor real estate is conserved, but reference-voltage-generator complexity increases

Engineering Contradiction:
Improvepacking densityVSAvoidcircuit complexity
Core Design Contradiction:
Quantity of substanceVSDevice complexity

Solution Approach 1:

The reference voltage generation circuit is segmented into multiple independent decks stacked vertically. Each deck contains a subset of the total resistive components and associated interconnect structures. This segmentation allows each individual deck to be simpler in design while the collective assembly achieves the required packing density. The segmentation also enables modular fabrication and assembly processes.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The interconnect structures serve multiple functions: they provide electrical connections between corresponding resistive components on adjacent decks, establish reference voltage pathways, and maintain structural integrity across the stacked assembly. This multi-functionality reduces the need for separate dedicated structures for each purpose, thereby managing complexity while achieving high packing density.

Inventive Principle:
Principle #6Universality (Multi-functionality)

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This configuration enables a more compact and efficient generation of reference voltages, enhancing packing density and allowing for tailored resistance values across switches, thereby improving the overall performance and efficiency of integrated circuits.

Implementation Method 1

The resistive components are coupled through switches to a feed line associated with a gain buffer. The switches may be utilized to control how many of the resistive components are electrically coupled to the feed line, and thus to control the VREF output from the gain buffer.

Methodology Applied
Scientific EffectElectrical Resistance: Electrical Resistance

Data Source

PatentUS11646073B2Reference-voltage-generators within integrated assemblies
Publication Date: 2023.05.09 MICRON TECHNOLOGY INC
  • US11646073B2 patent drawing
  • US11646073B2 patent drawing
  • US11646073B2 patent drawing

AI summary

Some embodiments include an integrated assembly having a deck over a base, and having memory cells supported by the deck. Each of the memory cells includes a capacitive unit and a transistor. The individual capacitive units of the memory cells each have a storage node electrode, a plate electrode, and a capacitor dielectric material between the storage node electrode and the plate electrode. A reference-voltage-generator includes resistive units supported by the deck. The resistive units are similar to the memory cells but include interconnecting units in place of the capacitive units. The interconnecting units of some adjacent resistive units are shorted to one another.