Stacked ReRAM Transistor Structure With Shared Source/Drain Scaling
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Solution Overview
Problem
The scaling of dynamic random-access memory (DRAM) technology is facing challenges due to retention time issues, necessitating the development of new memory technologies, and existing resistive random-access memory (ReRAM) devices require separate transistors for forming, set, and reset operations, leading to area penalties in integration.
Innovation Solution
The formation of ReRAM structures with stacked transistors, where a first transistor and a second transistor are vertically stacked with a shared source/drain region, allowing the top transistor to have a lower threshold voltage for high performance and the bottom transistor to handle the higher voltage needed for the forming event, thereby improving area scaling.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If DRAM technology is scaled down to increase memory density, then memory capacity increases, but retention time deteriorates
Solution Approach 1:
The patent transitions from volatile DRAM to non-volatile ReRAM by changing the fundamental storage parameter from charge-based to resistance-based storage. This parameter change enables data retention without power while maintaining high density through the emerging ReRAM technology.
Solution Approach 2:
The patent replaces the mechanical/electrical charge-based DRAM storage mechanism with a resistive storage mechanism in ReRAM devices, substituting the underlying physical principle to achieve both high density and non-volatility.
2Ease of manufacture
If traditional planar transistor structures are used, then manufacturing is simpler, but area utilization is insufficient for high-density memory
Solution Approach 1:
The patent transitions from planar 2D transistor structures to vertically stacked 3D transistor structures. This dimensional change allows multiple transistors to share common source/drain regions in the vertical dimension, dramatically improving area utilization while maintaining manufacturing feasibility through adapted fabrication processes.
Solution Approach 2:
The patent merges multiple transistor source/drain regions into shared common source/drain structures. By combining regions that would traditionally be separate in planar devices, the stacked configuration reduces total area while enabling efficient integration with ReRAM devices.
3Ease of operation
If separate source/drain regions are used for each transistor, then transistor operation is independent, but area consumption increases
Solution Approach 1:
The patent merges source/drain regions to be shared between multiple stacked transistors and the ReRAM device. This merging reduces area consumption by eliminating redundant regions while the vertical stacking maintains sufficient electrical independence for proper transistor operation.
Solution Approach 2:
The shared source/drain region serves multiple functions simultaneously: it acts as a source/drain for the first transistor, a source/drain for the second transistor, and an electrode for the ReRAM device. This multi-functionality reduces area consumption while maintaining operational independence.
Data Source
AI summary
A semiconductor structure comprises a first transistor, a second transistor vertically stacked over the first transistor, a source/drain region shared between the first transistor and the second transistor, and a resistive random-access memory device connected to the shared source/drain region.