Stacked ReRAM Access Structure for Sneak Path Current Suppression

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Solution Overview

Problem

Current ReRAM devices face challenges with sneak path currents and leakage currents through half-selected devices, which limit the size of crossbar arrays and contribute to high power consumption.

Innovation Solution

The proposed solution involves stacking ReRAM devices with access devices using a single patterning step, creating a stack with an access device formed on the ReRAM device or vice versa, and using sidewall spacers and dielectric layers to enhance the voltage window for sensing.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Quantity of substance

If ReRAM devices are arranged in large crossbar arrays, then memory capacity increases, but sneak path currents and leakage currents increase

Engineering Contradiction:
Improvememory capacityVSAvoidsneak path currents and leakage currents
Core Design Contradiction:
Quantity of substanceVSObject-generated harmful factors

Solution Approach 1:

The patent divides the crossbar array into smaller modular units by introducing access device stacks that segment the array into distinct regions. Each region is independently controlled by access devices, allowing selective activation and deactivation of specific segments to prevent sneak path currents from propagating across the entire array.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

Access device stacks serve as intermediary elements between the bit lines and word lines in the crossbar array. These access devices act as controlled switches that mediate current flow, enabling precise control over which memory cells are accessed and blocking unwanted current paths through half-selected devices.

Inventive Principle:
Principle #24Intermediary (Mediator)

2Object-generated harmful factors

If access devices are added to control ReRAM devices, then sneak path currents are reduced, but device complexity increases

Engineering Contradiction:
Improvesneak path currentsVSAvoidstacked device structure
Core Design Contradiction:
Object-generated harmful factorsVSDevice complexity

Solution Approach 1:

The patent transitions from a planar two-dimensional crossbar array to a three-dimensional stacked architecture. By adding the vertical dimension with multiple layers of ReRAM devices and access devices stacked together, the design achieves better control over current paths without requiring additional lateral space or complex routing.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

Solution Approach 2:

The patent combines multiple functional elements into integrated stacks where access devices and ReRAM devices are vertically coupled. This merging of control and memory functions into unified stacks reduces the overall footprint and simplifies the interconnect structure compared to separate planar implementations.

Inventive Principle:
Principle #5Merging (Combining)

3Ease of manufacture

If conventional planar ReRAM devices are used, then manufacturing is simpler, but density scaling is limited

Engineering Contradiction:
Improveplanar fabrication processVSAvoiddevice density
Core Design Contradiction:
Ease of manufactureVSQuantity of substance

Solution Approach 1:

The patent employs vertical stacking to achieve three-dimensional integration, allowing multiple memory layers to be stacked above each other. This dimensional transition enables significant density scaling by utilizing the vertical space above the substrate, multiplying the effective memory capacity without increasing the lateral footprint.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

Data Source

PatentUS12284922B2Stacked access device and resistive memory
Publication Date: 2025.04.22 INTERNATIONAL BUSINESS MACHINE CORPORATION
  • US12284922B2 patent drawing
  • US12284922B2 patent drawing
  • US12284922B2 patent drawing

AI summary

A semiconductor device including stacked access device and resistive memory includes a stack disposed on a base structure, the stack including an access device stack and a resistive random-access memory (ReRAM) device stack, sidewall spacers disposed along a portion of the stack, a dielectric layer disposed over the stack, the sidewall spacers and the base structure, and an interlevel dielectric disposed on the dielectric layer.