Stacked Resistance Element for High ESD Withstand
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Solution Overview
Problem
Existing resistance elements face challenges in increasing resistance value while maintaining sufficient electrostatic discharge (ESD) withstand capacity without altering the mounting area, and in accommodating varying chip sizes in semiconductor modules.
Innovation Solution
A resistance element comprising multiple vertically stacked chips with a semiconductor substrate, field insulating film, resistance layers, interlayer insulating film, pad forming electrodes, relay wiring, and back surface electrodes, where the uppermost pad forming electrode is connected to the lowermost back surface electrode to form a resistor, allowing for adjustable resistance values without changing the mounting area.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If the width of the resistor is narrowed in a single chip to increase resistance, then the resistance value increases, but the ESD withstand capacity becomes insufficient
Solution Approach 1:
The resistance element is divided into multiple chips stacked vertically, with each chip containing a resistance layer. This segmentation allows the total resistance to be distributed across multiple components while each individual chip maintains sufficient width for ESD withstand capacity. The series connection of resistance layers across chips achieves high resistance without narrowing the width of any single resistance layer.
Solution Approach 2:
The invention transitions from a single-chip planar configuration to a multi-chip vertical stacking configuration. By utilizing the vertical dimension (stacking chips in the thickness direction), the design achieves high resistance values without constraining the horizontal width of individual resistance layers, thereby preserving ESD withstand capacity in each chip.
2Manufacturing precision
If different chip sizes are used to achieve different resistance values, then the resistance value can be adjusted, but the mounting area in the semiconductor module must be changed
Solution Approach 1:
The resistance element is segmented into multiple standardized chips that can be stacked vertically. By varying the number of chips in the stack rather than changing the size of individual chips, different resistance values are achieved while maintaining a consistent mounting footprint. Each chip has standardized dimensions, allowing flexible resistance configuration without altering the overall mounting area.
Solution Approach 2:
The invention utilizes the vertical stacking dimension to achieve resistance value variation instead of changing the horizontal planar dimensions of the chips. By stacking a variable number of identically-sized chips vertically, the resistance value can be adjusted (through series connection of resistance layers) while the mounting area remains constant, as the horizontal footprint is determined by the chip planar shape rather than the number of stacked chips.
3Manufacturing precision
If multiple resistance chips are stacked vertically, then the resistance value can be increased while maintaining ESD capacity, but the device structure becomes more complex
Solution Approach 1:
The resistance element is segmented into multiple identical or similar chips with standardized structures. Each chip contains a resistance layer, insulating films, and electrodes arranged in a consistent pattern. This modular segmentation allows systematic stacking and simplifies manufacturing processes, as the same fabrication procedures can be applied to each chip. The repetitive structure reduces design complexity compared to creating entirely different single-chip configurations for different resistance values.
Solution Approach 2:
Each resistance chip is designed with a universal standardized structure that can serve multiple functions: providing resistance, withstanding ESD, and enabling vertical stacking through standardized electrode configurations. The pad forming electrodes and back surface electrodes are arranged to facilitate both electrical connection and mechanical stacking. This universal design allows the same chip structure to be used for various resistance values by simply varying the number of stacked chips, reducing overall device complexity.
Data Source
AI summary
A resistance element includes a plurality of resistance chips stacked vertically, each of the plurality of resistance chips including a semiconductor substrate, one or more resistance layers on a field insulating film, a pad forming electrode on electrically connected to the one or more resistance layers, a relay wiring on the interlayer insulating film, laterally separated from the pad forming electrode, electrically connected to another end of at least one of the one or more resistance layers on one end and to a semiconductor substrate on another end, and a back surface electrode at a bottom of the semiconductor substrate, making ohmic contact with the semiconductor substrate, wherein the plurality of resistance chips have the same planar outer shape, and are stacked one over another so as to constitute a resistor as a whole.