Stacked Resistance Layers for Compact IC Integration
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Solution Overview
Problem
Integrated circuit devices face challenges in accommodating resistance devices with large resistance values or multiple resistance selections without occupying excessive area, as existing resistance devices are bulky and inefficient in terms of integration density.
Innovation Solution
A semiconductor device design featuring stacked resistance layers and conductive plugs, allowing for the creation of a vertical multilayer resistance device structure that enables large resistance values within a compact area, with the resistance layers and plugs formed using conductive materials and shared deposition processes with select gates, enabling flexible resistance selection and high integration density.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If a resistance device with large resistance value or multiple resistance selections is provided, then the resistance function is improved, but the area occupied increases excessively
Solution Approach 1:
The patent transitions from a planar resistance structure to a vertical three-dimensional structure by stacking multiple resistance layers (first resistance layer 151, second resistance layer 152, third resistance layer 153) on top of each other. This vertical stacking enables multiple resistance values to be achieved within a compact footprint area, directly resolving the contradiction between resistance adaptability and area occupation.
Solution Approach 2:
The resistance device is segmented into multiple independent resistance layers (151, 152, 153) that can be selectively connected through different plug configurations. Each resistance layer provides a distinct resistance value, and by segmenting the overall resistance function into these discrete layers, the device achieves multiple resistance selections without requiring a large area for a single continuous resistance structure.
2Quantity of substance
If more resistance layers are stacked to achieve large resistance, then the resistance value increases, but the device complexity increases
Solution Approach 1:
The stacked resistance layers are formed using the same deposition process and material composition as the select gates (lower select gate, control gates, upper select gate). This multi-functionality approach allows the resistance layers to be created during the same manufacturing process sequence as the memory cell gates, reducing overall process complexity despite the increased structural complexity of having multiple resistance layers.
Solution Approach 2:
The patent merges the formation of resistance layers with the formation of select gates by using identical deposition processes and materials. The first resistance layer comprises material from the same deposition process as the lower select gate, and the uppermost resistance layer comprises material from the same deposition process as the upper select gate, thereby combining two functional structures into a unified manufacturing flow.
Data Source
AI summary
A semiconductor device includes a semiconductor substrate comprising a cell region and a peripheral circuit region, a first resistance layer and a second resistance layer spaced apart from each other and sequentially stacked on the semiconductor substrate of the peripheral circuit region, a first plug connected to the first resistance layer, and a second plug connected to the first and second resistance layers in common.