3D Stacked Resistance Memory for High Integration
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Solution Overview
Problem
Conventional resistance variable memory arrays face limitations in high integration due to the pitch of transistors and the need for shared source lines, which hinders further density and integration improvements.
Innovation Solution
A three-dimensional memory array structure is implemented where multiple variable resistance elements are stacked vertically, sharing one transistor, and each transistor's gate is connected to a word line, allowing for high integration and density by also integrating a diode to suppress interference and sneak currents.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If source lines are shared by multiple memory cells to improve integration, then device complexity is reduced, but interference and sneak currents increase
Solution Approach 1:
The patent transitions from a planar two-dimensional layout to a three-dimensional stacked architecture. Multiple variable resistance elements are stacked vertically above a single transistor, enabling one transistor to control multiple memory cells in the vertical dimension. This dimensional change allows higher integration density while maintaining proper signal isolation through the stacked configuration and selective word line activation.
Solution Approach 2:
The memory array is segmented into multiple independent variable resistance elements stacked vertically, each representing a separate memory cell. Each stacked element can be independently selected and accessed through the transistor gate control, allowing individual read/write operations on specific cells while others remain isolated, thereby reducing interference and sneak currents between cells.
2Productivity
If transistor size is reduced to increase integration density, then productivity increases, but manufacturing precision requirements worsen
Solution Approach 1:
By stacking variable resistance elements vertically in the third dimension, the patent achieves higher integration density without further reducing the lateral transistor pitch. This vertical stacking approach decouples the integration density metric from the transistor dimensional scaling, allowing larger, more manufacturable transistors while still achieving high cell density through the stacked configuration.
3Reliability
If bit lines and source lines are disposed in one-to-one relationship with swapped symmetry for bipolar memory, then reliability improves, but device complexity increases
Solution Approach 1:
The transistor serves multiple functions: it acts as a selection switch for the stacked variable resistance elements and also provides the necessary polarity control for bipolar write operations. The gate control mechanism universally handles both cell selection and write polarity determination, eliminating the need for separate dedicated source lines with swapped symmetry while maintaining reliable bipolar write operations.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration enables higher integration and density of memory arrays while effectively managing interference and sneak currents, enhancing the memory array's performance and capacity.
Implementation Method 1
A resistance variable memory uses a variable resistance element to store data in a reversible and non-volatile manner. Writing a variable resistance element to a low resistance state is called set (SET), and writing it to a high resistance state is called reset (RESET).
Implementation Method 2
A memory cell MC includes a variable resistance element and a transistor connected in series therewith. The gate of the transistor is electrically connected to the word line; the drain region is electrically connected to one electrode of the variable resistance element; the source region is electrically connected to the source line
Implementation Method 3
each gate of transistors in a row direction is commonly connected to a word line
Data Source
AI summary
The disclosure provides a resistance variable memory that can realize high integration. The resistance variable memory of the disclosure includes a plurality of transistors formed on a surface of a substrate, and a plurality of variable resistance elements stacked on the surface of the substrate in a vertical direction. One electrode of each of the variable resistance elements is commonly electrically connected to one electrode of one transistor, and another electrode of each of the variable resistance elements is respectively electrically connected to a bit line, and another electrode of each of the transistors is electrically connected to a source line, and each gate of transistors in a row direction is commonly connected to a word line.