Stacked Resistance Variable Memory Tile Control
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Solution Overview
Problem
Next-generation memory devices require high integration and low power consumption without periodic refresh, which existing resistance variable memory devices have not adequately addressed, particularly in terms of efficient stacking and control of word and bit lines in memory cell arrays.
Innovation Solution
A resistance variable memory device with a stacked structure of multiple decks and tiles, where word lines and bit lines are sequentially stacked, and decoding circuits control specific levels of word and bit lines to enable efficient memory operations, allowing for high integration and reduced power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If a stacked memory cell structure with multiple decks is implemented, then integration density is improved, but device complexity increases due to multiple word line and bit line levels requiring coordination
Solution Approach 1:
The memory device is divided into multiple independent decks (first deck with first and second word lines, second deck with third and fourth word lines), where each deck can be controlled separately through selective connection to bit lines. This segmentation allows high integration density while managing complexity through modular independence.
Solution Approach 2:
The patent implements a three-dimensional stacked structure with multiple decks stacked vertically, transitioning from planar to vertical arrangement. Word lines and bit lines are arranged in multiple levels (first word line, second word line, third word line, fourth word line across different decks), enabling high integration density through spatial dimensionality while maintaining controllability through selective electrical connections.
2Quantity of substance
If multiple levels of word lines and bit lines are stacked, then memory capacity is improved, but power consumption increases due to more control lines and switching elements
Solution Approach 1:
The patent employs dynamic control of word line connections through switching elements (transistors) that selectively connect or disconnect word lines from bit lines based on operational needs. The first word line can be selectively connected to first bit line, first word line to second bit line, second word line to first bit line, or second word line to second bit line, enabling power-efficient operations by activating only necessary line combinations.
Solution Approach 2:
The memory device is divided into multiple independent decks (first deck with first and second word lines, second deck with third and fourth word lines), where each deck can be controlled separately through selective connection to bit lines. This segmentation allows high integration density while managing complexity through modular independence.
3Measurement precision
If decoding circuits control specific levels of word and bit lines in selected tile regions, then operational precision is improved, but device complexity increases due to multiple decoding circuits
Solution Approach 1:
The memory array is divided into multiple tile regions (first tile region, second tile region, third tile region, fourth tile region), with each tile region having its own decoding circuit. This segmentation enables precise local control within each tile while distributing the control complexity across multiple independent decoding circuits rather than requiring one complex centralized controller.
Solution Approach 2:
Multiple decoding circuits are used, with each decoding circuit capable of controlling word lines and bit lines in its associated tile region. The decoding circuits perform universal functions (decoding row and column addresses, activating selected memory cells) across different tile regions, reducing overall system complexity through functional repetition and modularity.
Data Source
AI summary
A resistance variable memory device may include a plurality of tiles in which memory cells are arranged. The first to third level of the word lines may be sequentially stacked on the plurality of tile regions with the decoding circuits along rows of the tile regions. A first level of the bit lines may be interposed between the first level of the word lines and the second level of the word lines. A first level of the bit lines may be extended along columns of the tile regions. The second level of the bit lines may be interposed between the second level of the word lines and the third level of the word lines. The second level of the bit lines may be extended along the columns of the tile regions. The first and third levels of the word lines at a selected row of a selected tile region among the tile regions and the second level of the bit lines at a selected column of the selected tile region may be controlled by a decoding circuit of the selected tile region. The second level of the word line at the selected row of the selected tile region and the first level of the bit line at the selected column of the selected tile region may be controlled by another decoding circuit of another tile region.