Stacked Resistive Memory Cells for High Integration Density
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Solution Overview
Problem
Existing electron charge control-based memory devices face limitations in increasing memory capacity and integration density, necessitating the development of next-generation memory devices with high capacity, speed, and low power consumption, such as resistive memory devices.
Innovation Solution
A stack type resistive memory device is manufactured using a semiconductor substrate with multiple resistive memory cells, each comprising a switching transistor and a resistive device layer, connected to a common source line and bit line, allowing for high integration density without being restricted by critical dimensions, and a method involving multiple layers and insulating layers to form these components.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If electron charge control-based memory devices are used, then memory capacity can be increased, but integration density reaches physical limits
Solution Approach 1:
The patent transitions from planar memory cell arrangement to a three-dimensional stacked architecture. Multiple memory cells are vertically stacked above each other, utilizing the vertical dimension to increase integration density. This allows more memory cells to be packed into the same footprint area without increasing lateral device complexity
2Quantity of substance
If more memory cells are integrated in confined space, then memory capacity increases, but manufacturing precision requirements increase
Solution Approach 1:
The memory device is segmented into multiple discrete stacked layers, each containing memory cells with their own switching transistors and resistive devices. This segmentation allows each layer to be manufactured and assembled independently, reducing the cumulative precision requirements compared to a monolithic structure
Data Source
AI summary
A resistive memory device capable of improving an integration density is provided. The resistive memory device includes a semiconductor substrate, a plurality of resistive memory cells configured to be stacked on the semiconductor substrate and insulated from one another, where each of the plurality of resistive memory cells includes a switching transistor and a resistive device layer electrically connected to the switching transistor, a common source line electrically connected to the plurality of stacked resistive memory cells, and a bit line electrically connected to the plurality of stacked resistive memory cells and being insulated from the common source line.